2010 International Symposium on Next Generation Electronics最新文献_第6页

A systematic design automation approach for flash ADCs 一种flash adc的系统设计自动化方法

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669195

Chun-Po Huang, Ying-Zu Lin, Cheng-Wu Lin, Ya-Ting Shyu, Soon-Jyh Chang

引用次数: 3

A low cost 2D graphics anti-aliasing rendering scheme 一种低成本的2D图形抗混叠渲染方案

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669160

Ting-Chi Tong, Yun-Nan Chang

引用次数: 5

Segmented Hybrid DPWM and tunable PID controller for digital DC-DC converters 数字DC-DC变换器的分段混合DPWM和可调PID控制器

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669174

A. Sun, M. T. Tan, L. Siek

引用次数: 5

Modeling the parasitic capacitance of ESD protection SCR to co-design matching network in RF ICs 模拟射频集成电路中ESD保护晶闸管的寄生电容以协同设计匹配网络

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669189

Chun-Yu Lin, M. Ker

引用次数: 1

Mobility enhancement on nano-strained NMOSFET with epitaxial silicon buffer layers 外延硅缓冲层增强纳米应变NMOSFET的迁移率

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669152

Mu-Chun Wang, R. Yang, W. Liao, Hsin-Chia Yang, Yi-Cheng Luo, Z. Hsieh, Heng-Sheng Huang

引用次数: 0

A new STI-type FinFET device structure for high-performance applications 用于高性能应用的新型sti型FinFET器件结构

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669142

Jyi-Tsong Lin, Po-Hsieh Lin, Y. Eng

引用次数: 3

Automatic generation of high-performance multiple-input XOR/XNOR circuits and its application in Advanced Encryption Standard (AES) 高性能多输入XOR/XNOR电路的自动生成及其在高级加密标准(AES)中的应用

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669194

Shen-Fu Hsiao, Chia-Sheng Wen, Ming-Yu Tsai, Ming-Chih Chen

引用次数: 4

A low power dual-mode pulse triggered flip-flop using pass transistor logic 采用通管逻辑的低功耗双模脉冲触发触发器

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669163

Jin-Fa Lin, M. Sheu, Peng-Siang Wang

引用次数: 4

A low complexity video coding for combining RFID and video surveillance with padding based DVC 一种将RFID与视频监控相结合的低复杂度视频编码

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669158

T. Lei, Shiunn-Jang Chern

{"title":"A low complexity video coding for combining RFID and video surveillance with padding based DVC","authors":"T. Lei, Shiunn-Jang Chern","doi":"10.1109/ISNE.2010.5669158","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669158","url":null,"abstract":"Radio frequency identification (RFID) tag has been extensively used in diverse applications, recently. For instance, we may use it to track freights on a warehouse, to catch a thief for lost luggage and to rapidly locate lost children or passengers who fail to arrive on time at the departure gates of major airport. It can also be employed for transmitting multimedia content (especially for video). Presently, many research works focus on designing the RFID tag with high transmission data rate. In this paper we present a new practical scheme, it integrates the video surveillance into RFID tag at range of 250 kbps data rate for video data transmission. We believe that has not been addressed before in the literature. Here the Distributed Video Coding (DVC) scheme is integrated into RFID tag, where the so-called padding-based DVC scheme, proposed by us recently, is deployed. It is known that the padding-based DVC scheme has the advantages of requiring very low complexity and achieving low bit rate. Via computer simulations we show that the proposed scheme can easily work at data rate less than 250 kbps, and achieve better performance (PSNR) than the conventional approaches.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132219878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

16-nm multigate and multifin MOSFET device and SRAM circuits 16nm多栅多鳍MOSFET器件和SRAM电路

2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669144

Hui-Wen Cheng, Yiming Li

{"title":"16-nm multigate and multifin MOSFET device and SRAM circuits","authors":"Hui-Wen Cheng, Yiming Li","doi":"10.1109/ISNE.2010.5669144","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669144","url":null,"abstract":"In this work, we explore the effects of the number of fins and fin structure on the device DC, dynamic behaviors, and random-dopant-induced characteristic fluctuations of multifin field effect transistor (FET) circuits. Multifin FETs with different fin aspect ratios [AR ≡ fin height (Hfin)/fin width (Wfin)] and a fixed channel volume are simulated in a three-dimensional device simulation and the simulation results are experimentally validated. The multi-fin FinFET (AR = 2) has better channel controllability than the multifin trigate (AR = 1) and multi-fin quasi-planar (AR = 0.5) FETs. A six-transistor (6T) static random access memory (SRAM) using multi-fin FinFETs also provides the largest static noise margin because it supports the highest transconductance in FinFETs. Although FinFETs have a large effective device width and driving current, their large gate capacitance limits gate delay. The transient characteristics of an inverter with multi-fin transistors are further examined, and compared with those of an inverter with single-fin transistors. The multi-fin inverter has a shorter delay because it is dominated by the driving current of the transistor. With respect to random-dopant-induced fluctuations, the multifin FinFET suppresses not only the surface potential but also its variation because it has a more uniform surface potential than the multifin trigate and quasi-planar FET, and so the effects of random dopants on the circuits are attenuated. The results of this study provide insight into the DC, and circuit characteristics of multifin transistors and associated random dopant fluctuations.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126009596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10