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2010 International Symposium on Next Generation Electronics最新文献

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Design of stimulus driver to suppress epileptic seizure with adaptive loading consideration 考虑自适应负荷抑制癫痫发作的刺激驱动设计
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669138
Wei-Ling Chen, Chun-Yu Lin, M. Ker
{"title":"Design of stimulus driver to suppress epileptic seizure with adaptive loading consideration","authors":"Wei-Ling Chen, Chun-Yu Lin, M. Ker","doi":"10.1109/ISNE.2010.5669138","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669138","url":null,"abstract":"The novel design with the adaptability prevents from unexpected stimulus current for medical safety, since the safety is the prime concern for human use. The prototype of the stimulus driver circuit for micro-stimulator used in implantable device is presented in this paper. For epilepsy control, the target of the driver is to output 30-µA stimulus currents, as the tissue impedance varies within 20∼200 kΩ. The driver composed of the output stage, adaptor, and control block, has been integrated in a chip. Fabricated in a 0.35-µm 3.3-V/24-V CMOS process, the performances of this novel design have been confirmed. The averaged power consumption of the driver was only 0.24∼0.56 mW under 800-Hz stimulation rate.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123680121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the capacitively coupled transmission channel for body network application 体网电容耦合传输信道的研究
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669133
Chun-Yi Li, Chua-Chin Wang, R. Rieger
{"title":"On the capacitively coupled transmission channel for body network application","authors":"Chun-Yi Li, Chua-Chin Wang, R. Rieger","doi":"10.1109/ISNE.2010.5669133","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669133","url":null,"abstract":"Intrabody communication using the human body as the transmission channel enables low-power wireless communication within a body area network. Using intelligent nodes it is expected that condensed information packets are transmitted between nodes reducing the data rate to a few kbit/s. This paper investigates the practical low-frequency transmission quality using capacitive signal coupling via custom-made electrodes. The coupled signal is conducted by the body and a 3 Vpp carrier amplitude enables practical transmission with a median bit error rate of around 20% (reduced to 2.5% with 5Vpp amplitude) using Manchester coding.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129794397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient VLSI architecture for convolutional code decoding 卷积码译码的高效VLSI架构
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669156
Yeu-Horng Shiau, Pei-Yin Chen, Hung-Yu Yang, Yi-Ming Lin, Shi-Gi Huang
{"title":"An efficient VLSI architecture for convolutional code decoding","authors":"Yeu-Horng Shiau, Pei-Yin Chen, Hung-Yu Yang, Yi-Ming Lin, Shi-Gi Huang","doi":"10.1109/ISNE.2010.5669156","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669156","url":null,"abstract":"In this paper, an efficient VLSI architecture for convolutional code decoding algorithm is presented. This algorithm locates all erroneous segments of the received sequence and then applies our proposed decoder to these segments only. Besides, the clock-gating technique is used to disable the non-working registers of our design to further reduce the power consumption efficiently with no bit error rate (BER) degradation. Experimental calculations indicate that our design yields more power reduction than the conventional Viterbi decoder.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130191030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A fast-transient low-dropout regulator with current-feedback-buffer (CFB) for SoC application 具有电流反馈缓冲器(CFB)的SoC应用的快速瞬态低差稳压器
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669170
Jia-Hui Wang, Chun-Hung Yang, Chien-Hung Tsai
{"title":"A fast-transient low-dropout regulator with current-feedback-buffer (CFB) for SoC application","authors":"Jia-Hui Wang, Chun-Hung Yang, Chien-Hung Tsai","doi":"10.1109/ISNE.2010.5669170","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669170","url":null,"abstract":"The design of a low-voltage fast-transient low-dropout regulator (LDR) with a current feedback buffer (CFB) for system-on-ship (SoC) applications is presented. When the CFB senses variation in the load current, it quickly controls the power transistor to achieve fast-transient and small output voltage variation. The proposed LDR has high current efficiency because the CFB can adjust the quiescent current at various load currents. A 1 V capacitor-less LDR with a 1.2 V power supply was fabricated in 0.35 µm CMOS technology. The CFB improves the current efficiency from 66.5% to 99% in light load.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123368495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A novel dual-channel body-tied MOSFET with self-aligned structure for analog/RF applications 一种新颖的双通道体系MOSFET，具有自对准结构，用于模拟/射频应用
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669155
Yi-Hsuan Fan, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai
{"title":"A novel dual-channel body-tied MOSFET with self-aligned structure for analog/RF applications","authors":"Yi-Hsuan Fan, Jyi-Tsong Lin, Y. Eng, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai","doi":"10.1109/ISNE.2010.5669155","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669155","url":null,"abstract":"In this study, we propose a novel bulkSi-based device called dual-channel body-tied (DCBT) MOSFET using the self-aligned process without any extra masks. It reveals that our proposed DCBT FET has excellent S.S., decreased Isd,leak, lower Rsd, reduced Jg,limit, smaller lattice temperature, and higher thermal stability when compared with its DC counterpart. And, for the first time, we will investigate the analog/RF performance of our proposed DCBT FET. According to the numerical simulation results, the BT scheme can gain the excellent RF performances, increased rO (+53%) and higher fT (+20%), compared with a non-BT scheme.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124483274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient VLSI design for SIFT feature description 高效的VLSI SIFT特征描述设计
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669202
Yi-Ming Lin, Chun-Hsien Yeh, Sheng-Hung Yen, Ching-Hsuan Ma, Pei-Yin Chen, C.-C. Jay Kuo
{"title":"Efficient VLSI design for SIFT feature description","authors":"Yi-Ming Lin, Chun-Hsien Yeh, Sheng-Hung Yen, Ching-Hsuan Ma, Pei-Yin Chen, C.-C. Jay Kuo","doi":"10.1109/ISNE.2010.5669202","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669202","url":null,"abstract":"The scale invariant feature transform (SIFT) is a very efficient algorithm to extract and describe distinctive invariant features from images, and usually applied for many image applications such as object recognition, robotic mapping, and navigation. In the SIFT computation, the complexity of the feature description is quite high. Hence, it is desirable to have an efficient VLSI architecture to compute the feature descriptor quickly. We first investigate the performance analysis for SIFT and then employ the proper hardware circuit to implement the feature description process. Besides, the pipelining technique is adopted to increase the speed of our design. Synthesis results show that the proposed circuit contains 555,062 transistors by using the TSMC 0.13µm cell library. It works with a clock rate of 200 MHz and can support the throughput rate of about 65300 SIFT descriptors per second in real time.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123501831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An efficient tagging point selection algorithm to facilitate OPC process 一种高效的标记点选择算法，便于OPC处理
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669192
Lih-Shyang Chen, Lian-Yong Lin, Jing-Jou Tang, Meng-Lieh Sheu, Yong-Zhi Chen
{"title":"An efficient tagging point selection algorithm to facilitate OPC process","authors":"Lih-Shyang Chen, Lian-Yong Lin, Jing-Jou Tang, Meng-Lieh Sheu, Yong-Zhi Chen","doi":"10.1109/ISNE.2010.5669192","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669192","url":null,"abstract":"The rapid advance of resolution enhancement technique (RET) has driven the integrated circuits to the nanometer-scale era. Optical proximity correction (OPC) is one of the RET techniques that can be employed to reshape the mask patterns for correcting the distortion due to the optical proximity effect (OPE). In this paper, an Optical Performance Index (OPI) is proposed as an evaluation criteria for OPC performance. Also, an efficient tagging point selection algorithm is developed to facilitate the OPC process. Based on the OPI and selection algorithm, the tagging points for OPC can be easily located on either the regular patterns, e.g., rectangle or polygon, or the irregular patterns such as convex or concave patterns. Experimental results show that the quantity of storage and computing time can be dramatically reduced.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117339476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dual-core virtual platform with QEMU and SystemC 双核虚拟平台与QEMU和SystemC
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669196
C. Peng, Li-Chuan Chang, Chih-Hung Kuo, Bin-Da Liu
{"title":"Dual-core virtual platform with QEMU and SystemC","authors":"C. Peng, Li-Chuan Chang, Chih-Hung Kuo, Bin-Da Liu","doi":"10.1109/ISNE.2010.5669196","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669196","url":null,"abstract":"Dual-core platforms are growing as a new industry trend as platforms with only one core cannot easily perform the diverse functions in current embedded system applications, such as smart phones. We establish an easy-to-use co-simulation dual-core virtual platform to validate the functionality of hardware and software jointly. In our platform, the hardware components are implemented by SystemC, and two ARM CPUs which are emulated by QEMU, executing the software functions. To control the data flow, BSD sockets are employed to deliver data to each component, including shared memory, hardware modules and QEMU. A thread controller is also built to handle the system thread between the different cores. We verify the dual-core virtual platform using an advanced H.264/AVC encoder SystemC model and a H.264/AVC decoder. The model is controlled by a QEMU emulated ARM CPU, and another ARM CPU executes the decoder flow.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116883069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Stress-induced capacitance approximation using ring oscillator delay 利用环形振荡器延迟进行应力感应电容近似
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669182
W. Chang, Jian-an Lin, Ming-Feng Li
{"title":"Stress-induced capacitance approximation using ring oscillator delay","authors":"W. Chang, Jian-an Lin, Ming-Feng Li","doi":"10.1109/ISNE.2010.5669182","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669182","url":null,"abstract":"This study proposes an approach to estimate parasitic capacitance shift under mechanical stress. The silicon-on-insulator n-/p- metal-oxide-semiconductor field-effect transistors (MOSFETs) and CMOS ring oscillators (ROs) were fabricated side by side in this study. External compressive stresses were applied on a <110> strained channel of n-/p-MOSFETs and ROs in longitudinal and transverse configurations. The modeling mobilities of CMOS ROs used the measurement results of n-/p-MOSFET to simulate their oscillation frequencies under external stresses. The frequency difference between the experiment and simulation indicates parasitic capacitance variation under stresses.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117016433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High speed and wide tuning range voltage-controlled ring oscillator in 0.18µm CMOS 高速和宽调谐范围的压控环形振荡器在0.18µm CMOS
2010 International Symposium on Next Generation Electronics Pub Date : 2010-12-17 DOI: 10.1109/ISNE.2010.5669187
Y. Tiao, Meng-Lieh Sheu, L. Tsao
{"title":"High speed and wide tuning range voltage-controlled ring oscillator in 0.18µm CMOS","authors":"Y. Tiao, Meng-Lieh Sheu, L. Tsao","doi":"10.1109/ISNE.2010.5669187","DOIUrl":"https://doi.org/10.1109/ISNE.2010.5669187","url":null,"abstract":"A differential delay cell with complementary current control to extend the control voltage range as well as the operation frequency is proposed for high speed and wide tuning range voltage-controlled ring oscillator (VCRO). The complementary current control mitigates the restriction that control voltage can not operate at full range in a conventional VCRO. A three-stage VCRO is constructed for verifying the proposed differential delay cell. The VCRO is implemented using 0.18-µm 1P6M CMOS process and 1.8V supply voltage. Measured results show that a wide operation frequency range from 8.36GHz to 1.29GHz is achieved for the full range control voltage from 0V to 1.8V. The measured phase noise is −105.59dBc/Hz at 1MHz offset from the 8.35GHz centre frequency and a figure of merit (FOM) is −165.3 dBc/Hz. The core area is 106µm×76.2µm.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"927 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127014671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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