{"title":"A new STI-type FinFET device structure for high-performance applications","authors":"Jyi-Tsong Lin, Po-Hsieh Lin, Y. Eng","doi":"10.1109/ISNE.2010.5669142","DOIUrl":null,"url":null,"abstract":"A new STI-type FinFET structure with its body region been connected is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. From the simulation results, the STI-type FinFET shows that the short-channel effects (SCEs) and the off-state leakage current are proved to be reduced because the threshold voltage (VTH) roll-off and the drain-induced barrier lowering (DIBL) are well controlled. For same reason, this new device also exhibits a higher transconductance (GM) and its GD also maintains a good electrical performance with no kink effect compared with the conventional FinFET. With extra body region under the gate layer, the lattice temperature is decreased, and a good capability of alleviating the thermal instability is also obtained.","PeriodicalId":412093,"journal":{"name":"2010 International Symposium on Next Generation Electronics","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Symposium on Next Generation Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISNE.2010.5669142","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A new STI-type FinFET structure with its body region been connected is demonstrated and characterized by using three-dimensional (3-D) numerical simulations. From the simulation results, the STI-type FinFET shows that the short-channel effects (SCEs) and the off-state leakage current are proved to be reduced because the threshold voltage (VTH) roll-off and the drain-induced barrier lowering (DIBL) are well controlled. For same reason, this new device also exhibits a higher transconductance (GM) and its GD also maintains a good electrical performance with no kink effect compared with the conventional FinFET. With extra body region under the gate layer, the lattice temperature is decreased, and a good capability of alleviating the thermal instability is also obtained.