2012 IEEE Computer Society Annual Symposium on VLSI最新文献_第6页

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates 基于全光可逆NOR门的马赫-曾德尔干涉仪

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.72

Saurabh Kotiyal, H. Thapliyal, Nagarajan Ranganathan

{"title":"Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates","authors":"Saurabh Kotiyal, H. Thapliyal, Nagarajan Ranganathan","doi":"10.1109/ISVLSI.2012.72","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.72","url":null,"abstract":"Reversible logic has promising applications in dissipation less optical computing, low power computing, quantum computing etc. Reversible circuits do not lose information, and there is a one to one mapping between the input and the output vectors. In recent years researchers have implemented reversible logic gates in optical domain as it provides high speed and low energy computations. The reversible gates can be easily fabricated at the chip level using optical computing. The all optical implementation of reversible logic gates are based on semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI). The Mach-Zehnder interferometer has advantages such as high speed, low power, easy fabrication and fast switching time. In the existing literature, the NAND logic based implementation is the only implementation available for reversible gates and functions. There is a lack of research in the direction of NOR logic based implementation of reversible gates and functions. In this work, we propose the NOR logic based all optical reversible gates referred as all optical TNOR gate and all optical PNOR gate. The proposed all optical reversible NOR logic gates can implement the reversible boolean logic functions with reduced optical cost and propagation delay compared to their implementation using existing all optical reversible NAND gates. The advantages in terms of optical cost and delay is illustrated by implementing 13 standard boolean functions that can represent all 256 possible combinations of three variable boolean function.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129871949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles 利用量子力学原理分析基于可逆逻辑的顺序计算结构

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.60

Matthew Morrison, Nagarajan Ranganathan

引用次数: 5

Synthesis of Multithreshold Threshold Gates 多阈值门限门的合成

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.58

Maciej Nikodem, Marek A. Bawiec, J. Biernat

引用次数: 0

A DFT Methodology for Repairing Embedded Memories of Large MPSoCs 修复大型mpsoc内嵌记忆体的DFT方法

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.17

Kunal P. Ganeshpure, S. Kundu

{"title":"A DFT Methodology for Repairing Embedded Memories of Large MPSoCs","authors":"Kunal P. Ganeshpure, S. Kundu","doi":"10.1109/ISVLSI.2012.17","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.17","url":null,"abstract":"Memory Built-In Self-Test (MBIST) is used to test large memories embedded in Multi-Processor System on Chip (MPSoC). With increase in memory size, memory repair becomes necessary to improve yield. Memory repair consists of complex offline analysis requiring (i) fault diagnosis and (ii) optimizing reconfiguration based on failure map and available spare resources. This paper presents an embedded repair scheme that uses resources within a MPSoC. The main challenge involves establishing integrity of such internal resources before they are used for repair. We propose a layered approach to testing that (i) tests local processor cache first and uses (ii) software based self-testing of limited processor functions using (iii) a small program loaded into a cache from tester, which then (iv) serves as a vehicle for memory repair. This repaired memory can store and run larger software-based self-test programs to test the remaining systems. Software simulation is used to demonstrate feasibility of the proposed DFT scheme and test methodology. The main advantages of this approach are (i) avoidance of memory testers that are typically necessary for memory repair, (ii) avoiding additional hardware to support repair by using existing resources and (iii) testing all components using a logic tester.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116203825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Hardware Comparison of the ISO/IEC 29192-2 Block Ciphers ISO/IEC 29192-2分组密码的硬件比较

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.25

Neil Hanley, Máire O’Neill

引用次数: 59

A Wide Band Locking Range Quarter-PhaseGenerator PLL Using 0.13um BiCMOS Technology 采用0.13um BiCMOS技术的宽带锁相范围四分之一相发生器锁相环

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.69

Xuelian Liu, J. McDonald

引用次数: 2

A Case Study in Developing an Efficient Multi-threaded EDA Parser: Synopsys SDF Parser 开发高效多线程EDA解析器的案例研究:Synopsys SDF解析器

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.78

Prakash Shanbhag, C. Gopalakrishnan, Saibal Ghosh

引用次数: 3

Adaptive Stackable 3D Cache Architecture for Manycores 多核自适应可堆叠3D缓存架构

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.36

E. Guthmuller, I. Panades, A. Greiner

引用次数: 10

Testing of Trusted CMOS Data Converters 可信CMOS数据转换器的测试

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.23

A. Srivastava, R. Soundararajan

引用次数: 1

A Novel Design of Secure and Private Circuits 一种新的安全专用电路设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.55

M. Gomathisankaran, A. Tyagi

引用次数: 3