{"title":"修复大型mpsoc内嵌记忆体的DFT方法","authors":"Kunal P. Ganeshpure, S. Kundu","doi":"10.1109/ISVLSI.2012.17","DOIUrl":null,"url":null,"abstract":"Memory Built-In Self-Test (MBIST) is used to test large memories embedded in Multi-Processor System on Chip (MPSoC). With increase in memory size, memory repair becomes necessary to improve yield. Memory repair consists of complex offline analysis requiring (i) fault diagnosis and (ii) optimizing reconfiguration based on failure map and available spare resources. This paper presents an embedded repair scheme that uses resources within a MPSoC. The main challenge involves establishing integrity of such internal resources before they are used for repair. We propose a layered approach to testing that (i) tests local processor cache first and uses (ii) software based self-testing of limited processor functions using (iii) a small program loaded into a cache from tester, which then (iv) serves as a vehicle for memory repair. This repaired memory can store and run larger software-based self-test programs to test the remaining systems. Software simulation is used to demonstrate feasibility of the proposed DFT scheme and test methodology. The main advantages of this approach are (i) avoidance of memory testers that are typically necessary for memory repair, (ii) avoiding additional hardware to support repair by using existing resources and (iii) testing all components using a logic tester.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A DFT Methodology for Repairing Embedded Memories of Large MPSoCs\",\"authors\":\"Kunal P. Ganeshpure, S. Kundu\",\"doi\":\"10.1109/ISVLSI.2012.17\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Memory Built-In Self-Test (MBIST) is used to test large memories embedded in Multi-Processor System on Chip (MPSoC). With increase in memory size, memory repair becomes necessary to improve yield. Memory repair consists of complex offline analysis requiring (i) fault diagnosis and (ii) optimizing reconfiguration based on failure map and available spare resources. This paper presents an embedded repair scheme that uses resources within a MPSoC. The main challenge involves establishing integrity of such internal resources before they are used for repair. We propose a layered approach to testing that (i) tests local processor cache first and uses (ii) software based self-testing of limited processor functions using (iii) a small program loaded into a cache from tester, which then (iv) serves as a vehicle for memory repair. This repaired memory can store and run larger software-based self-test programs to test the remaining systems. Software simulation is used to demonstrate feasibility of the proposed DFT scheme and test methodology. The main advantages of this approach are (i) avoidance of memory testers that are typically necessary for memory repair, (ii) avoiding additional hardware to support repair by using existing resources and (iii) testing all components using a logic tester.\",\"PeriodicalId\":398850,\"journal\":{\"name\":\"2012 IEEE Computer Society Annual Symposium on VLSI\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-08-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Computer Society Annual Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2012.17\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2012.17","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A DFT Methodology for Repairing Embedded Memories of Large MPSoCs
Memory Built-In Self-Test (MBIST) is used to test large memories embedded in Multi-Processor System on Chip (MPSoC). With increase in memory size, memory repair becomes necessary to improve yield. Memory repair consists of complex offline analysis requiring (i) fault diagnosis and (ii) optimizing reconfiguration based on failure map and available spare resources. This paper presents an embedded repair scheme that uses resources within a MPSoC. The main challenge involves establishing integrity of such internal resources before they are used for repair. We propose a layered approach to testing that (i) tests local processor cache first and uses (ii) software based self-testing of limited processor functions using (iii) a small program loaded into a cache from tester, which then (iv) serves as a vehicle for memory repair. This repaired memory can store and run larger software-based self-test programs to test the remaining systems. Software simulation is used to demonstrate feasibility of the proposed DFT scheme and test methodology. The main advantages of this approach are (i) avoidance of memory testers that are typically necessary for memory repair, (ii) avoiding additional hardware to support repair by using existing resources and (iii) testing all components using a logic tester.