2012 IEEE Computer Society Annual Symposium on VLSI最新文献

Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design 基于STT-RAM的三维堆叠高速缓存热效应分析与优化

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.56

Xiuyuan Bi, Hai Helen Li, Jae-Joon Kim

{"title":"Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design","authors":"Xiuyuan Bi, Hai Helen Li, Jae-Joon Kim","doi":"10.1109/ISVLSI.2012.56","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.56","url":null,"abstract":"Spin-Transfer Torque Random Access Memory (STT-RAM) has been proved a promising emerging nonvolatile memory technology suitable for many applications such as cache memory of CPU. Simulation results show that the switching time of Magnetic Tunnel Junction (MTJ), which is the core element of the STT-RAM cell, varies when the temperature changes. In this paper, we study the thermal effect on switching time of STT-RAM cell, and it is showed that when temperature changes from 300K to 375K, the required write pulse period to achieve 10-8 bit error rate (BER) increases from 10.02ns to 15.04ns under 45nm technology. When STT-RAM is used as 3-D stacked L3 cache, the required write pulse period ranges from 11.42ns to 14.68ns due to temperature variation caused by the CPU core layer. If the thermal effect is not considered, the BER of the hottest region will significantly increase to 10-4. Based on these observations, an optimization design with Dynamic Temperature Aware Write Access is proposed, to increase the efficiency of accessing a 3-D stacked STT-RAM cache, as well as achieve the target BER. Compared to a conventional design, the proposed scheme can improve the CPU performance by 3.8% and reduce the write energy consumption of the STT-RAM cache by 4.8%.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115224201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A Tuneable CMOS Pulse Generator for Detecting the Cracks in Concrete Walls 用于混凝土墙体裂缝检测的可调谐CMOS脉冲发生器

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.20

T. Rao, A. Dutta, S. Singh, Arijit De, B. D. Sahoo

引用次数: 3

A Survey of Microarchitecture Support for Embedded Processor Security 嵌入式处理器安全的微体系结构支持综述

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.64

A. Kanuparthi, R. Karri, Gaston Ormazabal, Sateesh Addepalli

引用次数: 6

A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies 利用垂直部分连接拓扑的3D-NoC路由器实现

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.19

M. Bahmani, Abbas Sheibanyrad, F. Pétrot, Florentine Dubois, Paolo Durante

引用次数: 36

A Fast Head-Tail Expression Generator for TCAM -- Application to Packet Classification 一种快速的TCAM正尾表达式生成器——在包分类中的应用

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.47

Infall Syafalni, Tsutomu Sasao

引用次数: 2

Binary Difference Based Test Data Compression for NoC Based SoCs 基于二进制差分的NoC soc测试数据压缩

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.26

Sanga Chaki, C. Giri, H. Rahaman

引用次数: 3

An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies CNTFET和QCA技术中二值伽罗瓦场并发错误检测的研究

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.57

M. Poolakkaparambil, J. Mathew, A. Jabir, S. Mohanty

{"title":"An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies","authors":"M. Poolakkaparambil, J. Mathew, A. Jabir, S. Mohanty","doi":"10.1109/ISVLSI.2012.57","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.57","url":null,"abstract":"Permanent and temporary transient faults are the main concern in modern very large scale integrated circuits (VLSI). The main reason for such high vulnerability of the modern integrated circuit is their high integration density. Miniaturization of devices resulted in scaling their properties along with their size and thus making them a subject to induced faults and permanent faults. As the research progresses towards shrinking the technology even further to 15nm or below with potential CMOS replacement strategies such as carbon nano-tube field effect transistors (CNTFET) and quantum cellular automata (QCA) cells, the notion of fault susceptibility increases even further. Owing to these facts, this paper investigates the performance of standard concurrent error detection (CED) scheme over CNTEFETs and QCA technologies using normal basis (NB) finite field multiplier circuit as a test bench. The results are then compared with their CMOS equivalents which are believed to be the first reported attempt to the best of the authors'knowledge. The detailed experimental analysis of CMOS with CNTFET design proves that the emerging technologies perform better for error tolerant designs in terms of area, power, and delay as compared to its CMOS equivalent.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"51 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133880564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Uncertain Model and Algorithm for Hardware/Software Partitioning 硬件/软件分区的不确定模型与算法

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.14

Yu Jiang, Hehua Zhang, Xun Jiao, Xiaoyu Song, W. Hung, M. Gu, Jiaguang Sun

引用次数: 32

Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs 基于MTJs的创新非易失性FPGA架构中的构建块

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.21

L. Montesi, Z. Zilic, T. Hanyu, D. Suzuki

引用次数: 5

Nano-PPUF: A Memristor-Based Security Primitive 纳米ppuf:一种基于忆阻器的安全原语

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.40

Jeyavijayan Rajendran, G. Rose, R. Karri, M. Potkonjak

引用次数: 103