2012 IEEE Computer Society Annual Symposium on VLSI最新文献_第2页

A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic Biochips 交叉参考数字微流控生物芯片中路由感知网络布局的新算法

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.33

P. Roy, Rupam Bhattacharjee, H. Rahaman, P. Dasgupta

{"title":"A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic Biochips","authors":"P. Roy, Rupam Bhattacharjee, H. Rahaman, P. Dasgupta","doi":"10.1109/ISVLSI.2012.33","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.33","url":null,"abstract":"Digital micro fluidic biochips (DMFB) represent a new generation lab-on-a-chip architecture based upon micromanipulation of droplets via a programmed external electric field by an individually addressable 2D electrode array. DMFBs are classified as: Direct addressing and Cross-referencing biochips. Cross-referencing biochip technology scales down the number of pins per chip drastically, thereby reducing the costs of manufacturing and testing. However, these chips face a serious issue in terms of electrode interference during simultaneous routing of droplets. In this paper, we propose a routing-aware zone-based detailed placement scheme that rearranges the droplet locations on a pre-synthesized Bioassay schematic. The objectives of the proposed scheme include (i) an improved routing in respect of less overall routing time, more cell utilization, less crossover with intelligent collision avoidance, and (ii) enhanced pin sharing overcoming the major issue of electrode interference for Cross-referencing biochips. Simulations are carried out on four test benches of Benchmark suite III, and the results obtained are encouraging.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"600 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115108011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures 面向温度和可靠性的多核体系结构仿真框架

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.22

S. Corbetta, Davide Zoni, W. Fornaciari

引用次数: 21

Formal Estimation of Worst-Case Communication Latency in a Network-on-Chip 片上网络中最坏情况通信延迟的形式化估计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.31

V. Palaniveloo, A. Sowmya

引用次数: 6

Compilation Accelerator on Silicon 基于硅的编译加速器

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.76

N. Venkateswaran, V. Srinivasan, R. Kannan, P. Thinakaran, R. Hariharan, B. Vasudevan, N. Nachiappan, Karthikeyan P. Saravanan, Aswinkumar Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V. Vignesh, Ravindhiran Mukundrajan

{"title":"Compilation Accelerator on Silicon","authors":"N. Venkateswaran, V. Srinivasan, R. Kannan, P. Thinakaran, R. Hariharan, B. Vasudevan, N. Nachiappan, Karthikeyan P. Saravanan, Aswinkumar Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V. Vignesh, Ravindhiran Mukundrajan","doi":"10.1109/ISVLSI.2012.76","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.76","url":null,"abstract":"Current day processors utilize a complex and finely tuned system software to map applications across their cores and extract optimal performance. However with increasing core counts and the rise of heterogeneity among cores, tremendous stress will be exerted on the software stack leading to bottlenecks and underutilization of resources. We propose an architecture for a Compilation Accelerator on Silicon (CAS) coupled with a hardware instruction scheduler to tackle the complexity involved in analyzing dependencies among instructions dynamically, accelerate machine code generation and obtain optimum resource utilization across the cores by effective and efficient scheduling. The CAS is realized as a two-level hierarchical subsystem employing the Primary Compiler on Silicon (PCOS) and Secondary Compiler on Silicon (SCOS) with the hardware instruction scheduler as an integral part of it. A comparative analysis with the conventional GCC compiler is presented for a real world brain modeling application and higher instruction generation rates along with improved scheduling efficiency is observed resulting in a corresponding increase in resource utilization.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128221184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Parametric Hierarchy Recovery in Layout Extracted Netlists 布局提取网表中的参数层次恢复

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.18

John Lee, Puneet Gupta, F. Pikus

引用次数: 0

A Dataflow Framework for DSP Algorithm Refinement 一种DSP算法优化的数据流框架

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.74

Youngsoo Kim, W. Alexander, W. Edmonson

引用次数: 1

Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit 动态任务调度单元的指令集体系结构扩展

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.51

Oliver Arnold, Benedikt Noethen, G. Fettweis

引用次数: 16

Variance Optimization of CMOS OpAmp Performances Using Experimental Design Approach 基于实验设计方法的CMOS运放性能方差优化

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.38

Arnab Khawas, S. Mukhopadhyay

引用次数: 0

On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators 基于环振子的温度不变物理不可克隆函数的设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.66

Raghavan Kumar, Vinay C. Patil, S. Kundu

{"title":"On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators","authors":"Raghavan Kumar, Vinay C. Patil, S. Kundu","doi":"10.1109/ISVLSI.2012.66","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.66","url":null,"abstract":"CMOS implementation of Physically Unclonable Functions (PUFs) facilitates a number of applications ranging from digital rights management, device authentication, counterfeit detection/prevention and cryptographic key generation. Key expectations from such PUF circuits are high (i) uniqueness and (ii) reliability. Uniqueness refers to differentiated responses over challenge-response pairs. Reliability demands unvarying responses under varying environmental conditions such as temperature, supply voltage and noise. This paper describes two methods for achieving the above goals in a ring oscillator based PUF. The first method exploits the negative temperature resistance property of n+ and p+ polysilicon placed as source feedback resistors to de-sensitize ring oscillators to temperature variations. The second method uses an optimized supply voltage (V'DD) to reduce the temperature sensitivity of delay based ring oscillator PUFs. We report an improvement in reliability of 16% by combining these methods. Further, we propose a temperature-invariant ring oscillator PUF architecture based on Serial-Input Serial-Output (SISO) topology. In the proposed design, the relative phase difference between two ring oscillators is translated to a digital response bit. We show that this phase difference based response generation is superior to frequency based response generation in terms of area and power.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131481565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Operation Dynamics in Phase-Change Memory Cells and the Role of Access Devices 相变存储单元的操作动力学及存取装置的作用

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.48

A. Faraclas, N. Williams, F. Dirisaglik, K. Cil, A. Gokirmak, H. Silva

引用次数: 15