Variance Optimization of CMOS OpAmp Performances Using Experimental Design Approach

Abstract

The effects of random variations in the fabrication process have increased significantly with the scaling of technology, causing analog circuit performance parameters to deviate from their expected values. This leads to parametric failure of I performances causing a significant loss of yield. In this work, we propose a statistical design flow, based on analytical equation based convex optimization and Response Surface Method (RSM)based experimental design technique to enhance the parametric yield of analog circuits. Stochastic MOSFET (SMOS) models are used for statistical simulation of circuits to capture the effect of process variation and mismatch in terms of performance parameter variation. The fitted quadratic response surface models for performance standard deviation are used to optimize device dimensions of a two-stage Cascode OpAmp to get a variance optimal design keeping other performance parameters as design constraints.