2012 IEEE Computer Society Annual Symposium on VLSI最新文献_第3页

Design of Quantum Circuits for Random Walk Algorithms 随机漫步算法的量子电路设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.45

A. Chakrabarti, Chia-Chun Lin, N. Jha

{"title":"Design of Quantum Circuits for Random Walk Algorithms","authors":"A. Chakrabarti, Chia-Chun Lin, N. Jha","doi":"10.1109/ISVLSI.2012.45","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.45","url":null,"abstract":"A quantum algorithm is defined by a sequence of operations that runs on a realistic model of quantum computation. Since the first quantum algorithm proposed by David Deutsch(1985), a large number of impressive quantum algorithms have been developed. Quantum random walks on a graph, which are analogous to classical stochastic walk, form the basis for some of the recent quantum algorithms that promise to significantly outperform existing classical random walk algorithms. Though research has been done on the application of quantum random walk to important computational problems, very little work has been done on its quantum circuit design. There are two types of quantum random walk algorithms: discrete-time and continuous-time. In this paper, we propose quantum circuit designs for both types of random walk algorithms that operate on various graphs. We consider in detail two important problems to which random walk algorithms are applicable: the triangle finding problem and binary welded tree problem. Though there exist a few research works related to quantum circuit design for random walk on graphs, to the best of our knowledge, the circuit designs we present here are first of their kind. We also provide an estimate of the quantum cost of these circuits for several physical machine descriptions (PMDs)of quantum systems, based on the number of quantum operations and execution cycles.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133849319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache 基于STT-RAM的混合缓存中迁移最小化的代码运动

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.84

Qing'an Li, Liang Shi, Jianhua Li, C. Xue, Yanxiang He

引用次数: 10

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies 新兴纳米技术可逆电路的设计、合成与测试

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.83

H. Thapliyal, N. Ranganathan

引用次数: 21

Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical Applications 元模型辅助的用于生物医学应用的OP-AMP的快速准确优化

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.11

Geng Zheng, S. Mohanty, E. Kougianos

引用次数: 9

A New Parallel Processor Architecture for Genus 2 Hyperelliptic Curve Cryptosystems 属2超椭圆曲线密码系统的一种新的并行处理器结构

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.24

Yuejian Fang, Zhonghai Wu

引用次数: 2

Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes 利用热管降低三维集成电路的温度变化

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.16

Kunal P. Ganeshpure, S. Kundu

{"title":"Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes","authors":"Kunal P. Ganeshpure, S. Kundu","doi":"10.1109/ISVLSI.2012.16","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.16","url":null,"abstract":"With the advent of 3D stacking, thermal hotspots have emerged as a significant concern, due to challenges involved in removing heat from the intervening layers. Use of thermal through silicon vias (TSVs) to transfer heat from one layer to the next has been proposed as a hotspot mitigation technique. However, thermal TSV placement directly at the hotspots, compete with other design objectives due to higher wiring congestion at those sites. This paper presents a novel temperature aware physical design methodology which consists of using auxiliary routing known as Heat Pipes, to transfer heat away from hot regions in 3D integrated circuits. Heat Pipe is dummy routing connecting hot and cold regions in the same or different layers using interconnects and thermal TSVs that are placed opportunistically away from the congested areas. In order to evaluate hotspot temperature reduction due to Heat Pipes, a thermal model to simulate the effect of metal interconnect on heat distribution in 3D integrated circuits has been developed. Results show that the proposed solution using Heat Pipes lead to a reduction of 1 to 2 Kelvin at the hotspots. It is well known that even a small reduction in temperature of hotspots may significantly reduce the need for dynamic thermal management, often leading to large gain in system performance.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117341684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits 逻辑综合对数字集成电路软错误率的影响

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.67

D. Limbrick

引用次数: 1

Soft-Error Probability Due to SET in Clock Tree Networks 时钟树网络中由SET引起的软错误概率

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.39

R. Chipana, E. Chielle, F. Kastensmidt, Jorge Tonfat, R. Reis

引用次数: 6

Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits RTN下的时间性能退化:纳米级电路的评估和缓解

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.35

Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang

引用次数: 7

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework 电力归一化系统级可靠性分析与评估框架

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.42

R. Shafik, B. Al-Hashimi, J. Mathew, D. Pradhan, S. Mohanty

{"title":"RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework","authors":"R. Shafik, B. Al-Hashimi, J. Mathew, D. Pradhan, S. Mohanty","doi":"10.1109/ISVLSI.2012.42","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.42","url":null,"abstract":"System-level reliability estimation is a crucial aspect in reliable design of embedded systems. Recently reported estimation techniques use separate measurements of power consumption and reliability to demonstrate the trade-offs between them. However, we will argue in this paper that such measurements cannot determine comparative reliability of system components with different power consumptions and hence a composite measurement of reliability and power consumption is required. Underpinning this argument, we propose a SystemC based system-level reliability analysis and estimation framework, RAEF, using a novel composite metric, power normalized reliability (PNR), defined as the ratio of reliability and power consumption. We show that PNR based estimation enables insightful reliability analysis of different system components. We evaluate the effectiveness of such estimation in RAEF using a case study of MPEG-2 decoder with four processing cores considering single-event upset (SEU) based soft error model. Using this setup, we analyze and compare PNR based estimation with existing reliability evaluations at different system hierarchies. Furthermore, we demonstrate the advantages of RAEF in assessing design choices highlighting the impact of voltage scaling and architecture allocation.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126889158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24