A New Parallel Processor Architecture for Genus 2 Hyperelliptic Curve Cryptosystems

Yuejian Fang, Zhonghai Wu
{"title":"A New Parallel Processor Architecture for Genus 2 Hyperelliptic Curve Cryptosystems","authors":"Yuejian Fang, Zhonghai Wu","doi":"10.1109/ISVLSI.2012.24","DOIUrl":null,"url":null,"abstract":"Hyper elliptic curve cryptosystem (HECC) is much more efficient than RSA and elliptic curve cryptosystem (ECC) for its shorter key lengths. Hyper elliptic curve cryptosystems can be sped up by parallel execution on hardware accelerators, yet none of previous efforts can sufficiently support parallel processing with reasonable resources. In this paper, we propose a new parallel processor architecture for HECC, which supports sufficient instruction-level parallel processing. In the architecture, Parallel finite field (FF) cores are designed, and each core consists of a control unit, a register file, an ALU and a ROM. Instruction-level parallelism (ILP) with pipeline is achieved in this architecture. The results show that the implementation can achieve much better performance than other hardware implementations done to date.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2012.24","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

Hyper elliptic curve cryptosystem (HECC) is much more efficient than RSA and elliptic curve cryptosystem (ECC) for its shorter key lengths. Hyper elliptic curve cryptosystems can be sped up by parallel execution on hardware accelerators, yet none of previous efforts can sufficiently support parallel processing with reasonable resources. In this paper, we propose a new parallel processor architecture for HECC, which supports sufficient instruction-level parallel processing. In the architecture, Parallel finite field (FF) cores are designed, and each core consists of a control unit, a register file, an ALU and a ROM. Instruction-level parallelism (ILP) with pipeline is achieved in this architecture. The results show that the implementation can achieve much better performance than other hardware implementations done to date.
属2超椭圆曲线密码系统的一种新的并行处理器结构
超椭圆曲线密码系统(HECC)具有较短的密钥长度,比RSA和椭圆曲线密码系统(ECC)更高效。超椭圆曲线密码系统可以通过在硬件加速器上并行执行来提高速度,但以往的努力都无法在合理的资源下充分支持并行处理。在本文中,我们提出了一种新的并行处理器架构,它支持足够的指令级并行处理。在该体系结构中,设计了并行有限域核(FF),每个核由一个控制单元、一个寄存器文件、一个ALU和一个ROM组成,实现了具有流水线的指令级并行性(ILP)。结果表明,该实现比目前其他硬件实现的性能要好得多。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信