2012 IEEE Computer Society Annual Symposium on VLSI最新文献_第4页

RRAM Motifs for Mitigating Differential Power Analysis Attacks (DPA) 减少差分功率分析攻击(DPA)的RRAM主题

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.68

Ganesh Khedkar, D. Kudithipudi

{"title":"RRAM Motifs for Mitigating Differential Power Analysis Attacks (DPA)","authors":"Ganesh Khedkar, D. Kudithipudi","doi":"10.1109/ISVLSI.2012.68","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.68","url":null,"abstract":"Hybrid Resistive Random Access Memory(RRAM)/CMOS architectures offer several opportunities in the next generation high performance systems. These systems are vulnerable to side channel attacks(SPA), including Differential Power Analysis (DPA) attacks. An architecture with cryptoco processors integrated on a dedicated CMOS layer and the associated memory on the RRAM layer, can help mitigate the side channel attacks on these systems. In particular, we focus on the DPA attacks which can compromise the system performance, by statistically analyzing information of intermediate results in a cryptographic computation. In this paper we propose the use of RRAM to obscure the power signals that mitigate the DPA attacks. RRAM motifs are dynamically reconfigurable hardware crossbar structures that can be programmed on-the-fly in to a memory or sensing elements. We investigate a 4x64 RRAMmotif that can perform memory and sensing in tandem. Our analysis shows that we cannot easily distinguish between the memory access and sensing operations. Though the power dissipated in the best and worst case scenarios when reading from an RRAM motif varied by 9%, it does not provide any additional information on the specific access. Additionally, it was observed that the variations in the voltage and temperature of the RRAM generate noise in guessing the sub key and enhances the DPA resiliency of the system.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127217968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability 虚拟化虚拟通道以提高片上网络的健壮性和可升级性

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.44

Marios Evripidou, C. Nicopoulos, V. Soteriou, Jongman Kim

引用次数: 26

Ultra Low Power Circuit Design Using Tunnel FETs 隧道场效应管超低功耗电路设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.70

Ravindhiran Mukundrajan, M. Cotter, V. Saripalli, M. J. Irwin, S. Datta, N. Vijaykrishnan

引用次数: 37

PTL: PCM Translation Layer PCM转换层

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.75

Z. Shao, N. Chang, N. Dutt

引用次数: 15

On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors 微处理器低成本电源噪声检测传感器的设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.32

Arunkumar Vijayakumar, Raghavan Kumar, S. Kundu

引用次数: 7

On-Chip Sample Preparation with Multiple Dilutions Using Digital Microfluidics 利用数字微流体进行多次稀释的片上样品制备

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.52

D. Mitra, Sudip Roy, K. Chakrabarty, B. Bhattacharya

{"title":"On-Chip Sample Preparation with Multiple Dilutions Using Digital Microfluidics","authors":"D. Mitra, Sudip Roy, K. Chakrabarty, B. Bhattacharya","doi":"10.1109/ISVLSI.2012.52","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.52","url":null,"abstract":"In many biochemical protocols, solution preparation is a preprocessing step for mixing two or more fluids in a given ratio. Dilution of a biochemical sample/reagent is the special case of mixing or solution preparation where only two different type of fluids, one of which is a buffer solution, are mixed at a certain ratio corresponding to the desired concentration factor. Bioassays implemented on digital micro fluidic biochips may require several different concentration values of the same sample/reagent. In this paper, we present a scheme in which a set of different target droplets (with concentration values ranged between 0% and 100%) can be produced with an acceptable error bound in minimum mix-split steps. The method does not require any intermediate storage since, at each step, the current droplet is mixed only with the sample (with 100% concentration) or with the buffer (with 0% concentration) droplet. The problem of generating multiple target concentrations has been formulated based on a binary de Bruijn graph. The proposed technique outperforms the existing single target based methods in terms of both the number of mix-split steps and the number of waste droplets. This in turn, reduces the execution time, the number of electrode actuations, and sample/reagent requirement. A digital micro fluidic platform can also be easily designed to implement such on-chip sample preparation.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121542851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs) 三维集成电路(3D ic)可靠供电系统设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.73

Pei-Wen Luo, Tao Wang, C. Wey, L. Cheng, Bih-Lan Sheu, Yiyu Shi

引用次数: 5

Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design 低功耗纳米cmos热传感器设计的随机梯度下降优化

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.13

Oghenekarho Okobiah, S. Mohanty, E. Kougianos, Oleg Garitselov, Geng Zheng

{"title":"Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design","authors":"Oghenekarho Okobiah, S. Mohanty, E. Kougianos, Oleg Garitselov, Geng Zheng","doi":"10.1109/ISVLSI.2012.13","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.13","url":null,"abstract":"The drive for ultra efficient and low-cost portable devices continues to push the need for low power circuit designs. The increasing transistor density and complexity of IC designs aggravates the task of producing efficient low power and low cost design. The short time to market (TTM) also increases this burden on designers, as optimal designs have to be produced in an ever decreasing amount of time. This paper presents an optimization design flow methodology that optimizes the power (accounting leakage) consumption of integrated circuits (ICs). The design flow incorporates a stochastic gradient descent (SGD) based algorithm and is implemented using a 45 nm thermal sensor circuit as case study. Power-efficient high-sensitive thermal sensors are important to reduce the burden on the systems or circuits that they are implanted to sense. Experiments are performed to apply the proposed design flow methodology on the thermal sensor with the power consumption as the design objective while keeping the temperature resolution as a constraint. Experiments on full-blown (RCLK) netlist of sense amplifier show a reduction in power consumption by 38%.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127811127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Novel Ternary-to-Binary Converter in Quantum-Dot Cellular Automata 量子点元胞自动机中一种新的三元到二元转换器

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.41

Mohsen M. Arjmand, M. Soryani, K. Navi, Mohammad A. Tehrani

引用次数: 10

Aging-Aware Instruction Cache Design by Duty Cycle Balancing 基于占空比平衡的指令缓存老化感知设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.30

Tao Jin, Shuai Wang

{"title":"Aging-Aware Instruction Cache Design by Duty Cycle Balancing","authors":"Tao Jin, Shuai Wang","doi":"10.1109/ISVLSI.2012.30","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.30","url":null,"abstract":"The degradation of CMOS devices over the lifetime can cause the severe threat to the system performance and reliability at deep sub micron semiconductor technologies. The negative bias temperature instability (NBTI) is among the most important sources of the aging mechanisms. Applying the traditional guard banding technique to address the decreased speed of devices is too costly. Due to the unbalanced duty cycle ratio of the SRAM cells, the instruction cache suffers a heavy NBTI stress and this will further exacerbate the aging effect in the instruction cache. In this paper, we propose an aging-aware design to combat the NBTI-induced aging in the instruction cache. First, the detailed lifetime behaviors of the cache lines in the instruction cache are studied. Then, different schemes are proposed to mitigate the negative aging effects by balancing the duty cycle ratio of the SRAM cells in the cache lines according to their different lifetime phases. By applying our proposed idle-time-based cache line invalidation and bit-flipping /complementing schemes, the duty cycle ratio of the instruction cache can be well balanced and the NBTI stress will be significantly reduced.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133755478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9