Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs)

Abstract

Three-dimensional integrated circuits (3D ICs) have drawn groundswell of interest in both academia and industry in recent years. However, the power integrity of 3D ICs is threatened by the increased current density brought by vertical integration. To enhance reliability, the locations of power/ground through-silicon-vias (P/G TSVs), which are used to deliver power/ground signals to different layers, must be carefully placed to minimize IR-drop. However, the currents in 3D ICs are not deterministic and exhibit both spatial and temporal correlations. In view of this, we propose a correlation based heuristic algorithm for P/G TSV placement. Unlike most existing works, the proposed algorithm does not need iterations of full-grid simulations. Thus, it is especially attractive for large designs with millions of nodes. Experimental results on TSMC 90nm industrial designs indicate that the proposed method can achieve up to 70% reduction in IR-drop compared with the current industry practice, which uniformly distributes P/G TSVs.