2012 IEEE Computer Society Annual Symposium on VLSI最新文献_第5页

SCOC IP Cores for Custom Built Supercomputing Nodes 用于自定义超级计算节点的SCOC IP内核

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.80

N. Venkateswaran, R. Hariharan, V. Srinivasan, R. Kannan, P. Thinakaran, Vigneshwaran Sankaran, B. Vasudevan, Ravindhiran Mukundrajan, N. Nachiappan, Aswinkumar Sridharan, Karthikeyan P. Saravanan, Vignesh Adhinarayanan, V. Sankaranarayanan

{"title":"SCOC IP Cores for Custom Built Supercomputing Nodes","authors":"N. Venkateswaran, R. Hariharan, V. Srinivasan, R. Kannan, P. Thinakaran, Vigneshwaran Sankaran, B. Vasudevan, Ravindhiran Mukundrajan, N. Nachiappan, Aswinkumar Sridharan, Karthikeyan P. Saravanan, Vignesh Adhinarayanan, V. Sankaranarayanan","doi":"10.1109/ISVLSI.2012.80","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.80","url":null,"abstract":"A high performance and low power node architecture becomes crucial in the design of future generation supercomputers. In this paper, we present a generic set of cells for designing complex functional units that are capable of executing an algorithm of reasonable size. They are called Algorithm Level Functional Units (ALFUs) and a suitable VLSI design paradigm for them is proposed in this paper. We provide a comparative analysis of many core processors based on ALFUs against ALUs to show the reduced generation of control signals and lesser number of memory accesses, instruction fetches along with increased cache hit rates, resulting in better performance and power consumption. ALFUs have led to the inception of the Super Computer On Chip (SCOC) IP core paradigm for designing high performance and low power supercomputing clusters. The proposed SCOC IP cores are compared with the existing IP cores used in supercomputing clusters to bring out the improved features of the former.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134396717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure 基于一种新型可逆逻辑结构的树型比较器和存储单元的设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.61

Matthew Morrison, Matthew Lewandowski, N. Ranganathan

{"title":"Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure","authors":"Matthew Morrison, Matthew Lewandowski, N. Ranganathan","doi":"10.1109/ISVLSI.2012.61","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.61","url":null,"abstract":"Programmable reversible logic is gain wide consideration as a logic design style for modern nanotechnology and quantum computing with minimal impact on circuit heat generation in improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Then, a novel 3*3 programmable UPG gate capable of calculating the universal logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fred kin gate is presented and verified. Next, a novel 4*4 reversible programmable RC gate capable of nine unique logical calculations at low cost and delay is presented and verified. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. These designs are compared to previously existing designs, and their advantages in terms of cost and delay are analyzed. Then, the RMUX is used to improve a reversible SRAM cell we previously presented. The memory cell and comparator are implemented in the design of a Min/Max Comparator device.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134045383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders 可逆纹波、前缀和前缀-纹波混合加法器的设计与分析

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.50

C. Vudadha, P. Phaneendra, Syed Ershad Ahmed, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas

引用次数: 4

A Compression-Based Hybrid MLC/SLC Management Technique for Phase-Change Memory Systems 基于压缩的相变存储系统混合MLC/SLC管理技术

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.62

H. Lee, Seungcheol Baek, Jongman Kim, C. Nicopoulos

引用次数: 30

Cross-Layer Techniques for Optimizing Systems Utilizing Memories with Asymmetric Access Characteristics 利用非对称存取特性存储器优化系统的跨层技术

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.65

Yong Li, A. Jones

引用次数: 5

Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits 地质统计启发的纳米cmos电路元建模与优化

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.12

Oghenekarho Okobiah, S. Mohanty, E. Kougianos

{"title":"Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits","authors":"Oghenekarho Okobiah, S. Mohanty, E. Kougianos","doi":"10.1109/ISVLSI.2012.12","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.12","url":null,"abstract":"With the continuous progression of semiconductor technology, nanoscale effects have become a persistent issue in the design of analog/mixed-signal (AMS) circuits. The cost of exploration and optimization of the design space increases to infeasible levels with conventional design methodologies. Different modeling techniques to reduce the cost of design exploration, while ensuring the accuracy of such models, have been introduced and continue to be a research problem. In this paper, a geostatistical inspired metamodeling and optimization technique is presented for fast and accurate design optimization of nano-CMOS circuits. The proposed design methodology incorporates a simple Kriging based metamodel which efficiently and accurately predicts design performance. The metamodel (instead of the circuit netlist) is subjected to a Gravitational Search Algorithm for optimization. This design methodology is applicable to AMS circuits and is illustrated with the optimization of power consumption of a 45nm CMOS thermal sensor. The method improves the power performance of the thermal sensor by 36.9% while reducing the design optimization time by 90% even with 6 design parameters.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116095877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories NVMain:用于新兴非易失性存储器的架构级主存储器模拟器

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.82

Matthew Poremba, Yuan Xie

引用次数: 155

Delay Analysis for an N-Input Current Mode Threshold Logic Gate n输入电流模式阈值逻辑门的延迟分析

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.34

Chandra Babu Dara, T. Haniotakis, S. Tragoudas

引用次数: 10

Data-Width-Driven Power Gating of Integer Arithmetic Circuits 数据宽度驱动的整数算术电路功率门控

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.59

T. Hoang, P. Larsson-Edefors

引用次数: 4

Design of Prefix-Based Optimal Reversible Comparator 基于前缀的最优可逆比较器设计

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.49

C. Vudadha, P. Phaneendra, S. Veeramachaneni, Syed Ershad Ahmed, N. Muthukrishnan, M. Srinivas

引用次数: 24