NVMain:用于新兴非易失性存储器的架构级主存储器模拟器

Matthew Poremba, Yuan Xie
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引用次数: 155

摘要

新兴的非易失性存储器(NVM)技术,如PCRAM和STT-RAM,已经显示出巨大的潜力,可以替代基于dram的计算机系统主存储器设计。对于计算机架构师来说,重要的是在架构级别对这些新兴的内存技术进行建模,以便更好地利用它们来提高未来计算系统的性能/能源/可靠性,从而了解其优点和局限性。在本文中,我们介绍了一个名为NV Main的架构级模拟器,它可以用DRAM和新兴的非易失性存储技术对主存储器设计进行建模,并可以帮助设计人员利用这些新兴的存储技术进行设计空间探索。我们讨论了模拟器的设计要点,并提供了模型的验证,以及使用该工具进行设计空间探索的案例研究。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
NVMain: An Architectural-Level Main Memory Simulator for Emerging Non-volatile Memories
Emerging non-volatile memory (NVM) technologies, such as PCRAM and STT-RAM, have demonstrated great potentials to be the candidates as replacement for DRAM-based main memory design for computer systems. It is important for computer architects to model such emerging memory technologies at the architecture level, to understand the benefits and limitations for better utilizing them to improve the performance/energy/reliability of future computing systems. In this paper, we introduce an architectural-level simulator called NV Main, which can model main memory design with both DRAM and emerging non-volatile memory technologies, and can facilitate designers to perform design space explorations utilizing these emerging memory technologies. We discuss design points of the simulator and provide validation of the model, along with case studies on using the tool for design space explorations.
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