{"title":"n输入电流模式阈值逻辑门的延迟分析","authors":"Chandra Babu Dara, T. Haniotakis, S. Tragoudas","doi":"10.1109/ISVLSI.2012.34","DOIUrl":null,"url":null,"abstract":"A recent approach is capable of identifying threshold logic functions with as many as fifty inputs with small integer weights on the inputs. An analytical method is presented for selecting optimum sensor sizes. This allows us to design large threshold functions with delay much less than a network of CMOS gates. Exhaustive SPICE simulations show that implemented TLGs by the proposed approach consistently exhibit behavior very close to the optimal.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"137 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Delay Analysis for an N-Input Current Mode Threshold Logic Gate\",\"authors\":\"Chandra Babu Dara, T. Haniotakis, S. Tragoudas\",\"doi\":\"10.1109/ISVLSI.2012.34\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A recent approach is capable of identifying threshold logic functions with as many as fifty inputs with small integer weights on the inputs. An analytical method is presented for selecting optimum sensor sizes. This allows us to design large threshold functions with delay much less than a network of CMOS gates. Exhaustive SPICE simulations show that implemented TLGs by the proposed approach consistently exhibit behavior very close to the optimal.\",\"PeriodicalId\":398850,\"journal\":{\"name\":\"2012 IEEE Computer Society Annual Symposium on VLSI\",\"volume\":\"137 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-08-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Computer Society Annual Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2012.34\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2012.34","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Delay Analysis for an N-Input Current Mode Threshold Logic Gate
A recent approach is capable of identifying threshold logic functions with as many as fifty inputs with small integer weights on the inputs. An analytical method is presented for selecting optimum sensor sizes. This allows us to design large threshold functions with delay much less than a network of CMOS gates. Exhaustive SPICE simulations show that implemented TLGs by the proposed approach consistently exhibit behavior very close to the optimal.