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2012 IEEE Computer Society Annual Symposium on VLSI最新文献

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Algorithms for On-Chip Solution Preparation Using Digital Microfluidic Biochips 利用数字微流控生物芯片制备片上溶液的算法
2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.79
Sudip Roy, P. Chakrabarti, B. Bhattacharya
{"title":"Algorithms for On-Chip Solution Preparation Using Digital Microfluidic Biochips","authors":"Sudip Roy, P. Chakrabarti, B. Bhattacharya","doi":"10.1109/ISVLSI.2012.79","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.79","url":null,"abstract":"Digital micro fluidic (DMF) biochips have recently emerged as a very new technology for health-care and biochemical laboratory applications, as they are inexpensive, sensitive, fully-automated, integrated systems. In a DMF biochip, on-chip and automatic solution preparation requires solving of some algorithmic problems. In this paper, we present some results of our proposed algorithms for on-ship solution preparation using DMF biochips.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127918241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable Functions 操纵制造变化以获得更好的硅基物理不可克隆功能
2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-01 DOI: 10.1109/ISVLSI.2012.28
Domenic Forte, Ankur Srivastava
{"title":"Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable Functions","authors":"Domenic Forte, Ankur Srivastava","doi":"10.1109/ISVLSI.2012.28","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.28","url":null,"abstract":"Physically Unclonable Functions (PUFs) provide interesting solutions to tnany security related issues. For instance, silicon-based PUFs are novel circuits that exploit manufacturing variations to extract unique signatures from chips. Such signatures are convenient for chip authentication and cryptographic key generation. Since variations are typically detrimental to ICs, a great deal of research is geared towards suppressing them. However, in the case of PUFs, it has been shown that wily systematic manufacturing variations are harmful and random manufacturing variations are actually the source of PUF quality. In this paper, we investigate two techniques that manipulate manufacturing variations to improve PUFs: (i) a cell layout technique that reduces systematic variation; (ii) a design technique that increases random variation. Results show that the layout technique improves PUF uniqueness by as much as 14% and the design technique improves PUF reliability by as much as 25%.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132258461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A Hardware Architecture for Image Clustering Using Spiking Neural Networks 一种基于脉冲神经网络的图像聚类硬件结构
2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-01 DOI: 10.1109/ISVLSI.2012.46
M. Nuño-Maganda, M. Arias-Estrada, C. Torres-Huitzil, H. H. Avilés-Arriaga, Y. Hernández-Mier, M. Morales-Sandoval
{"title":"A Hardware Architecture for Image Clustering Using Spiking Neural Networks","authors":"M. Nuño-Maganda, M. Arias-Estrada, C. Torres-Huitzil, H. H. Avilés-Arriaga, Y. Hernández-Mier, M. Morales-Sandoval","doi":"10.1109/ISVLSI.2012.46","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.46","url":null,"abstract":"Spiking Neural Networks (SNNs) have become an important research theme due to new discoveries and advances in neurophysiology, which states that information among neurons is interchanged via pulses or spikes. FPGAs are widely used for implementing high performance digital hardware systems, due to its flexibility and because they are suitable for the implementation of systems with high degree of parallelism. FPGAs have become an important tool because fine grain digital elements useful for efficient hardware implementation of SNNs are provided, making FPGA device suitable for implementing SNNs. SNNs are less hardware greedy, and the nature of the pulsed processing is well suited to the digital processing blocks of the FPGA devices. Several computer vision applications have been implemented using SNNs. One of the most critical tasks in computer vision is image clustering. In this paper, a hardware architecture for implementing image clustering using SNNs is reported. Results and performance statistics are provided.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116848867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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