2012 IEEE Computer Society Annual Symposium on VLSI最新文献_第7页

0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI 0.18 um CMOS工艺高灵敏度差分光可重构门阵列VLSI

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.71

Takahiro Watanabe, Minoru Watanabe

引用次数: 0

Protecting CRT RSA against Fault and Power Side Channel Attacks 保护CRT RSA免受故障和电源侧通道攻击

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.54

A. Fournaris, O. Koufopavlou

{"title":"Protecting CRT RSA against Fault and Power Side Channel Attacks","authors":"A. Fournaris, O. Koufopavlou","doi":"10.1109/ISVLSI.2012.54","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.54","url":null,"abstract":"The RSA cryptographic algorithm is a security tool that has achieved long cryptographic and market maturity. However, after the discovery and wide spread of Side Channel Attacks (SCA), RSA implementations are susceptible to a variety of different attacks that target the hardware structure rather than the algorithm itself. While there are a wide range of countermeasures that can be applied on the RSA structure in order to protect the algorithm from specific SCA categories, combining several such measures to produce an \"all in one\" SCA resistant RSA structure is not an easy endeavor. Several incompatibility issues between combined SCA protection methods lead to new SCA vulnerabilities. In this paper, we evaluate some very popular and potent SCAs against RSA, like Fault attacks (FA), Simple Power attacks (SPA), Doubling attacks (DA) and Differential Power attacks (DPA), and propose an SCA protection scheme for RSA based on Chinese Remainder Theorem (CRT) that can thwart them. The proposed scheme uses a square and always multiply approach in combination with the message blinding technique in such a way that possible vulnerabilities that may rise from this combination can no longer apply. The proposed scheme is evaluated against specific SCAs and is found to be very secure. From performance point of view, the proposed scheme favors parallelism and can calculate an RSA result with small time delay.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114905835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic 基于hdl的可逆逻辑合成中的线路最小化

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.43

R. Wille, Mathias Soeken, Eleonora Schönborn, R. Drechsler

引用次数: 16

Methodology for Efficient Multi-threading of Parsers in EDA Tools EDA工具中高效多线程解析器的方法

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.77

Prakash Shanbhag, C. Gopalakrishnan, Saibal Ghosh

引用次数: 2

Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm SHA-512哈希算法展开硬件架构的吞吐量和效率分析

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.63

I. Algredo-Badillo, M. Morales-Sandoval, C. F. Uribe, R. Cumplido

{"title":"Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm","authors":"I. Algredo-Badillo, M. Morales-Sandoval, C. F. Uribe, R. Cumplido","doi":"10.1109/ISVLSI.2012.63","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.63","url":null,"abstract":"In order to design efficient hardware implementations of cryptographic algorithms for a particular application, it is often required to explore several architectures in order to select the one that offers the appropriate trade-off between throughput and hardware resources. A natural choice for performing a design space exploration are the Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. In this paper we explore several architectures for implementing the SHA-512 algorithm based on the loop unrolling technique and analyze their area-performance trade-offs. The analysis consists on unrolling at different levels the main loop which is the most costly part in the SHA-512 algorithm. The resulting hardware architectures are implemented and analyzed in order to identify the critical path and make decisions on the architectural design. The obtained results provide a practical guide to understand the effect of introducing different levels (1, 2, 4, 5, 8) of unrolling in terms of throughput and hardware resources. The hardware architecture 4x that partially unrolls four iterations of the main loop of the SHA-512 algorithm reports the best performance compared against related works, while the 1x architecture exhibits the best efficiency.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134329824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Utilizing PCM for Energy Optimization in Embedded Systems 利用PCM进行嵌入式系统的能量优化

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.81

Z. Shao, Yongpan Liu, Yiran Chen, Tao Li

{"title":"Utilizing PCM for Energy Optimization in Embedded Systems","authors":"Z. Shao, Yongpan Liu, Yiran Chen, Tao Li","doi":"10.1109/ISVLSI.2012.81","DOIUrl":"https://doi.org/10.1109/ISVLSI.2012.81","url":null,"abstract":"Due to its high density, bit alterability, and low standby power, phase change memory (PCM) is considered as a promising DRAM alternative. In embedded systems, especially battery-driven mobile devices, energy is one of the most important performance metrics. Therefore, it becomes an interesting problem of utilizing PCM for energy optimization in embedded systems. While recently there have been extensive studies on PCM, energy optimization with PCM in embedded systems has not been fully addressed. In this paper, we present a hybrid memory system architecture in which PCM is used to replace DRAM as much as possible so the system energy can be reduced by utilizing the lower standby power of PCM. However, to achieve this, system-level software optimization techniques are required in order to solve problems caused by the three disadvantages of PCM: namely, long write latency, large write energy and limited write endurance. We propose an optimal static data allocation scheme to solve a simplified problem, and discuss how to extend this to solve more complex problems. We also present emerging research issues in compiler optimization, real-time task scheduling and operating systems when utilizing PCM for energy optimization in embedded systems.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131047581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

Hybrid 3D-IC Cooling System Using Micro-fluidic Cooling and Thermal TSVs 采用微流体冷却和热tsv的混合3D-IC冷却系统

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.29

Bing Shi, Ankur Srivastava, A. Bar-Cohen

引用次数: 43

VLSI Design and Implementation of Homophonic Security System 谐音安全系统的VLSI设计与实现

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.37

N. Sklavos, P. Kitsos, O. Koufopavlou

引用次数: 7

Understanding the Switching Mechanism in Transition Metal Oxide Based ReRAM Devices 基于过渡金属氧化物的ReRAM器件开关机制的研究

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.53

R. Jha, B. Long

引用次数: 0

An Improvement in Partial Order Reduction Using Behavioral Analysis 用行为分析改进偏序约简

2012 IEEE Computer Society Annual Symposium on VLSI Pub Date : 2012-08-19 DOI: 10.1109/ISVLSI.2012.15

Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, C. Myers

引用次数: 4