0.18 um CMOS工艺高灵敏度差分光可重构门阵列VLSI

Takahiro Watanabe, Minoru Watanabe
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摘要

目前,对可编程器件进行高速动态重构以提高其性能的需求日益增加。为了支持高速动态重构,光可重构门阵列(ORGAs)得到了迅速的发展。此外,为了进一步提高重构速度,采用不同配置环境下的差分重构方法的光差分可重构门阵列(ODRGAs)已经被开发出来。ODRGA包括全息存储器、激光阵列和光学可重构门阵列VLSI。全息存储器可以存储许多配置上下文。它的大带宽光连接使高速重构成为可能。然而,传统ODRGAs的光电二极管灵敏度并不好。因此,本文提出了一种新的0.18 um CMOS工艺光差分可重构门阵列VLSI芯片,具有高灵敏度的光电路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI
Currently, demand is increasing for high-speed dynamic reconfiguration on programmable devices to improve their performance. To support high-speed dynamic reconfiguration, optically reconfigurable gate arrays (ORGAs) have been undergoing rapid development. Moreover, to more increase the reconfiguration speed, optically differential reconfigurable gate arrays (ODRGAs) incorporating a differential reconfiguration method between configuration contexts have been developed. An ODRGA comprises a holographic memory, a laser array, and an optically reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. Its large-bandwidth optical connection enables high-speed reconfiguration. However, photodiode sensitivities of conventional ODRGAs are not good. This paper therefore presents a newly fabricated 0.18 um CMOS process optically differential reconfigurable gate array VLSI chip with highly sensitive photo-circuits.
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