Throughput and Efficiency Analysis of Unrolled Hardware Architectures for the SHA-512 Hash Algorithm

In order to design efficient hardware implementations of cryptographic algorithms for a particular application, it is often required to explore several architectures in order to select the one that offers the appropriate trade-off between throughput and hardware resources. A natural choice for performing a design space exploration are the Field Programmable Gate Arrays (FPGAs) for being reconfigurable, flexible and physically secure devices. In this paper we explore several architectures for implementing the SHA-512 algorithm based on the loop unrolling technique and analyze their area-performance trade-offs. The analysis consists on unrolling at different levels the main loop which is the most costly part in the SHA-512 algorithm. The resulting hardware architectures are implemented and analyzed in order to identify the critical path and make decisions on the architectural design. The obtained results provide a practical guide to understand the effect of introducing different levels (1, 2, 4, 5, 8) of unrolling in terms of throughput and hardware resources. The hardware architecture 4x that partially unrolls four iterations of the main loop of the SHA-512 algorithm reports the best performance compared against related works, while the 1x architecture exhibits the best efficiency.