{"title":"逻辑综合对数字集成电路软错误率的影响","authors":"D. Limbrick","doi":"10.1109/ISVLSI.2012.67","DOIUrl":null,"url":null,"abstract":"Reliability-aware synthesis exploits the properties of fault masking to improve the reliability of logic circuits. My dissertation investigates how synthesis constraints can impact the effectiveness of this technique.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits\",\"authors\":\"D. Limbrick\",\"doi\":\"10.1109/ISVLSI.2012.67\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Reliability-aware synthesis exploits the properties of fault masking to improve the reliability of logic circuits. My dissertation investigates how synthesis constraints can impact the effectiveness of this technique.\",\"PeriodicalId\":398850,\"journal\":{\"name\":\"2012 IEEE Computer Society Annual Symposium on VLSI\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-08-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Computer Society Annual Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2012.67\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2012.67","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits
Reliability-aware synthesis exploits the properties of fault masking to improve the reliability of logic circuits. My dissertation investigates how synthesis constraints can impact the effectiveness of this technique.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
