{"title":"采用0.13um BiCMOS技术的宽带锁相范围四分之一相发生器锁相环","authors":"Xuelian Liu, J. McDonald","doi":"10.1109/ISVLSI.2012.69","DOIUrl":null,"url":null,"abstract":"This paper presents a quarter-phase 32GHz PLL using 0.13um SiGe BiCMOS technology for a high speed microprocessor. The PLL characterizes a 3-state phase frequency detector (PFD), a charge pump loop filter, a VCO, a frequency doubler and a feedback 1/32 frequency divider. The VCO used in this PLL is a four -- stage ring oscillator that has a wide tuning range with a feed-forward interpolation topology for coarse frequency tuning and varactor diodes load capacitance variation for fine frequency tuning. The PLL has a wide locking range from 24.4 GHz to 39 GHz with a phase noise of-102dBc/Hz at 1MHz offset.","PeriodicalId":398850,"journal":{"name":"2012 IEEE Computer Society Annual Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Wide Band Locking Range Quarter-PhaseGenerator PLL Using 0.13um BiCMOS Technology\",\"authors\":\"Xuelian Liu, J. McDonald\",\"doi\":\"10.1109/ISVLSI.2012.69\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a quarter-phase 32GHz PLL using 0.13um SiGe BiCMOS technology for a high speed microprocessor. The PLL characterizes a 3-state phase frequency detector (PFD), a charge pump loop filter, a VCO, a frequency doubler and a feedback 1/32 frequency divider. The VCO used in this PLL is a four -- stage ring oscillator that has a wide tuning range with a feed-forward interpolation topology for coarse frequency tuning and varactor diodes load capacitance variation for fine frequency tuning. The PLL has a wide locking range from 24.4 GHz to 39 GHz with a phase noise of-102dBc/Hz at 1MHz offset.\",\"PeriodicalId\":398850,\"journal\":{\"name\":\"2012 IEEE Computer Society Annual Symposium on VLSI\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-08-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE Computer Society Annual Symposium on VLSI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2012.69\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE Computer Society Annual Symposium on VLSI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2012.69","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Wide Band Locking Range Quarter-PhaseGenerator PLL Using 0.13um BiCMOS Technology
This paper presents a quarter-phase 32GHz PLL using 0.13um SiGe BiCMOS technology for a high speed microprocessor. The PLL characterizes a 3-state phase frequency detector (PFD), a charge pump loop filter, a VCO, a frequency doubler and a feedback 1/32 frequency divider. The VCO used in this PLL is a four -- stage ring oscillator that has a wide tuning range with a feed-forward interpolation topology for coarse frequency tuning and varactor diodes load capacitance variation for fine frequency tuning. The PLL has a wide locking range from 24.4 GHz to 39 GHz with a phase noise of-102dBc/Hz at 1MHz offset.
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