Testing of Trusted CMOS Data Converters

Abstract

In this work, we present testing of trusted CMOS data converters using DeltaIDDQ and on-chip linear ramp histogram techniques. DeltaIDDQ technique can be efficiently used to detect faults taking process variation into effect. We present design for an on-chip testability of CMOS analog-to-digital converter using linear-ramp histogram technique. The paper discusses a brief overview of the histogram technique, the formulae used to calculate the ADC parameters, the design implemented in 0.5μm n-well CMOS process, the results and effectiveness of the design. The on-chip linear ramp histogram technique can be seamlessly combined with DeltaIDDQ technique for improved testability, increased fault coverage and reliable operation.