2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)最新文献_第8页

Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicide CMOS technology 1.8 v 0.15-/spl mu/m部分耗尽SOI盐化CMOS工艺中CMOS器件ESD稳健性研究

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934478

M. Ker, Kei-Kang Hong, Tung-Yang Chen, H. Tang, S. Huang, S.-S. Chen, C. Huang, M. Wang, Y. Loh

引用次数: 3

On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process 基于亚四分之一微米CMOS工艺多晶硅二极管的GHz射频集成电路片上ESD保护设计

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934529

C. Chang, M. Ker

引用次数: 8

New insights into breakdown modes and their evolution in ultra-thin gate oxide 超薄栅极氧化物击穿模式及其演变的新见解

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934477

H. Lin, D. Lee, C. Lee, T. Chao, T. Huang, T. Wang

引用次数: 11

Nanoscale CMOS at low temperature: design, reliability, and scaling trend 低温下的纳米级CMOS:设计、可靠性和缩放趋势

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934473

B. Yu, H. Wang, C. Riccobene, Hyeon-Seag Kim, Q. Xiang, M. Lin, Leland Chang, C. Hu

引用次数: 12

Electrical and physical characterization of high-k dielectric layers 高k介电层的电学和物理特性

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934518

M. Houssa, M. Naili, V. Afanas'ev, M. Heyns, A. Stesmans

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引用次数: 8

Ultrathin ox/nitride gate stack for sub-quarter-micron CMOS devices prepared by RTCVD 用RTCVD制备亚四分之一微米CMOS器件的超薄氧化/氮化栅极堆

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934521

M. Wang, C. Chen, M.C. Yu, T. Hou, Y.M. Lin, S.C. Chcn, Y. Fang, C. Yu, M. Liang

引用次数: 0

ESD protection strategy for sub-quarter-micron CMOS technology: gate-driven design versus substrate-triggered design 亚四分之一微米CMOS技术的ESD保护策略:栅极驱动设计与衬底触发设计

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934527

Tung-Yang Chen, M. Ker

引用次数: 7

A 50 nm vertical Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/ pMOSFET with an oxide/nitride gate dielectric 一个50 nm垂直Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/ pMOSFET，具有氧化物/氮化栅极电介质

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934470

P. Verheyen, N. Collaert, M. Caymax, R. Loo, M. Van Rossum, K. De Meyer

引用次数: 1