一个50 nm垂直Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/ pMOSFET，具有氧化物/氮化栅极电介质

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI:10.1109/VTSA.2001.934470

P. Verheyen, N. Collaert, M. Caymax, R. Loo, M. Van Rossum, K. De Meyer

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引用次数: 1

摘要

在应变弛缓的Si/sub 0.85/Ge/sub 0.15/缓冲层上，制备了具有Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/源层的垂直减压化学气相沉积(RP-CVD)异质结pMOS晶体管，通道长度可达50 nm。本文报道了该源栈在该信道长度区域抑制短信道效应的可行性。这是通过比较垂直Si/sub 0.85/Ge/sub 0.15/同质结晶体管和垂直Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/异质结晶体管的电特性来完成的，通道长度为90 nm和50 nm。

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A 50 nm vertical Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/ pMOSFET with an oxide/nitride gate dielectric

Vertical Reduced Pressure Chemical Vapour Deposition (RP-CVD) grown heterojunction pMOS transistors with a Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/ source stack have been fabricated with channel lengths down to 50 nm on a strain relaxed Si/sub 0.85/Ge/sub 0.15/ buffer layer. This paper reports on the viability of this source stack to suppress short channel effects in this channel length region. This is done by comparing the electrical characteristics of vertical Si/sub 0.85/Ge/sub 0.15/ homojunction transistors, and vertical Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/ heterojunction transistors, with channel lengths of 90 nm and 50 nm.

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来源期刊

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

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