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2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)最新文献

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High quality interpoly dielectrics deposited on the nitrided-polysilicon for nonvolatile memory devices 用于非易失性存储器件的氮化多晶硅上沉积的高质量插补介电体
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-07-01 DOI: 10.1109/VTSA.2001.934503
T. Chao, W. Yang, Chun-Ming Cheng, T. Pan, T. Lei
{"title":"High quality interpoly dielectrics deposited on the nitrided-polysilicon for nonvolatile memory devices","authors":"T. Chao, W. Yang, Chun-Ming Cheng, T. Pan, T. Lei","doi":"10.1109/VTSA.2001.934503","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934503","url":null,"abstract":"In this study, a NH/sub 3/ with RTA N/sub 2/O process to incorporate nitrogen at dielectric/polysilicon interface has demonstrated an improvement in the integrity of the polyoxide. The polyoxide deposited on these nitrided polysilicon films with the additional N/sub 2/O densification on TEOS exhibits a lower leakage current, higher electric breakdown field, higher electron barrier height, lower electron trapping rate, and much higher charge-to-breakdown than the as-deposited polyoxide. SIMS result shows the incorporation of nitrogen at the polyoxide/poly-1 interface, which improves electrical properties in return. Polyoxides formed by this method can achieve a high breakdown field up to 19 MV/cm and charge-to-breakdown more than 20 C/cm/sup 2/. This process appears to be a very attractive alternative for conventional polyoxides.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131084256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low voltage CMOS fully differential active inductor and its application to RF bandpass amplifier design 低压CMOS全差动有源电感及其在射频带通放大器设计中的应用
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934499
A. Thanachayanont
{"title":"Low voltage CMOS fully differential active inductor and its application to RF bandpass amplifier design","authors":"A. Thanachayanont","doi":"10.1109/VTSA.2001.934499","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934499","url":null,"abstract":"This paper presents the design of a 1.5 V CMOS fully-differential inductorless RF bandpass amplifier using a 0.35 /spl mu/m n-well CMOS technology. The bandpass amplifier employs a p-channel input cascode transconductor and the newly proposed low-voltage fully-differential active inductor as an active tuned load. HSPICE simulation of the bandpass amplifier operating at a centre frequency of 1 GHz and a quality factor of 50 illustrates that a voltage gain of 50 dB and a noise figure of 4.2 dB can be achieved with a power dissipation of 46 mW from a single 1.5 V power supply voltage.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126847224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A lithographically-friendly 6F/sup 2/ DRAM cell 一个光刻友好的6F/sup / DRAM单元
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934492
S. Bukofsky, J. Mandelman, A. Thomas, C. Radens, G. Kunkel
{"title":"A lithographically-friendly 6F/sup 2/ DRAM cell","authors":"S. Bukofsky, J. Mandelman, A. Thomas, C. Radens, G. Kunkel","doi":"10.1109/VTSA.2001.934492","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934492","url":null,"abstract":"Ever-decreasing chip size in successive generations of DRAM has been largely achieved by lithographic ground rule scaling. Recently, a combination of device performance issues and uncertainty in future lithographic scaling have led to the investigation of novel array cell architectures, as well as fundamental changes in the array transistor itself. These new cell architectures present a unique challenge for optical lithography, especially when implemented at aggressive ground rules. In this paper, we discuss how lithography can influence the design of a DRAM array cell, and present lithographic results from a 512 Mb, 6F/sup 2/ DRAM technology practiced at 0.13 /spl mu/m ground rules. We discuss the methodology of \"lithography-friendly\" cell design in the context of sub-8F/sup 2/ arrays, and describe a multiple exposure technique for capacitor formation in the sub-8F/sup 2/ regime.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129364919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and implementation of a routing switch for irregular interconnection networks 不规则互连网络路由交换机的设计与实现
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934486
Hsin-Chou Chi, Chia-Ming Wu
{"title":"Design and implementation of a routing switch for irregular interconnection networks","authors":"Hsin-Chou Chi, Chia-Ming Wu","doi":"10.1109/VTSA.2001.934486","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934486","url":null,"abstract":"We present the design and implementation of a routing switch for irregular interconnection networks, which can be used to construct workstation clusters. A routing architecture we previously proposed for irregular interconnection networks, called TRAIN (tree-based routing architecture for irregular networks), is described. The VLSI implementation of a switch design for TRAIN is then presented.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-speed bit-parallel systolic multipliers for a class of GF(2/sup m/) 一类GF(2/sup m/)的高速位并行收缩乘法器
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934542
Chiou-Yng Lee, E. Lu, Jau-Yien
{"title":"High-speed bit-parallel systolic multipliers for a class of GF(2/sup m/)","authors":"Chiou-Yng Lee, E. Lu, Jau-Yien","doi":"10.1109/VTSA.2001.934542","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934542","url":null,"abstract":"Two special operations, called the cyclic shifting and the inner product are defined based on the properties of irreducible all one polynomials. With the two operations, an effective algorithm for computing multiplication over a class of GF(2/sup m/) was developed in this paper. The low-complexity bit-parallel systolic multipliers are presented. The multiplier is composed of (m+1)/sup 2/ identical cells, each of which consisting of one 2-bit AND gate, one 2-bit XOR gate and three 1-bit latches. The multiplier has very low latency and propagation delay, which makes them very fast. Moreover the architectures of the multiplier can also be applied to compute multiplication over the class of GF(2/sup m/) in which the elements are represented with the root of an irreducible equally spaced polynomial degree.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133003023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Wireless systems-on-a-chip design 无线片上系统设计
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934479
R. Brodersen, W. R. Davis, D. Yee, Ning Zhang
{"title":"Wireless systems-on-a-chip design","authors":"R. Brodersen, W. R. Davis, D. Yee, Ning Zhang","doi":"10.1109/VTSA.2001.934479","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934479","url":null,"abstract":"There is a fundamental shift that is occurring in the implementation of wireless systems. Not only is the underlying technology shifting to mainstream CMOS technology, but the applications and specifications of the supported links is also rapidly evolving. These two trends result in radical shifts in the radio system architectures, which ranges from the implementation issues associated with the analog RF circuitry and the digital baseband processing to the basic techniques for dealing with multi-access and the impairments of the channel. All of these design issues are driven by an ever-widening range of requirements from the high bandwidth needs of multimedia Internet access to the ultra low power needs of sensor data networks. The multiple inter-related technologies required for implementation of such wireless system requires a co-design strategy in communication algorithms, protocols, digital architectures as well the analog and digital circuits required for their implementation. A design infrastructure which achieves this is described, which has a particular emphasis on methods for high level specification and estimation, that provides a fully automated chip design flow.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115911160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
System on a chip: a system perspective 片上系统:系统视角
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934467
G. Frantz
{"title":"System on a chip: a system perspective","authors":"G. Frantz","doi":"10.1109/VTSA.2001.934467","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934467","url":null,"abstract":"Technology advances are providing us with an overwhelming capability to create new products that will impact the way we work, live, learn and play. Integrated circuits are getting smaller and at the same time are faster, lower in cost and lower in power dissipation. We are, at the same time, integrating more on to a single device. The ability to put a complete system on one device is now a practical option. But, with the ability to create a complete \"System On a Chip\" (SOC) there comes the responsibility to do it wisely. The remainder of this paper will take a system's perspective of SOC. First, a quick look back at several examples of SOC. Then a discussion of why and how one should use SOC technology. Finally, a discussion on whom should design SOC.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116945197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Threshold-voltage anomaly in sub-0.2 /spl mu/m DRAM buried-channel pFET devices 低于0.2 /spl mu/m的DRAM埋道pet器件的阈值电压异常
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934471
C. Murthy, R. Katsumata, S. Inaba, R. Rengarajan, P. Oldiges, P. Ronsheim
{"title":"Threshold-voltage anomaly in sub-0.2 /spl mu/m DRAM buried-channel pFET devices","authors":"C. Murthy, R. Katsumata, S. Inaba, R. Rengarajan, P. Oldiges, P. Ronsheim","doi":"10.1109/VTSA.2001.934471","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934471","url":null,"abstract":"Measurements and simulation have been used to study threshold-voltage (V/sub t/) dependence on gate oxide thickness (t/sub ox/) for long-channel buried-channel (BC-) pFET devices in sub-0.2 /spl mu/m CMOS technologies. The combination of the dual gate oxide process using N/sub 2/ implantation to create the thinner gate oxide and well RTA results in the thinner t/sub ox/ devices having higher V/sub t/, contrary to expectation (V/sub t/-t/sub ox/ anomaly). Detailed analysis of doping profiles, depletion contours, and electric potential confirms this anomaly both in the enhancement and depletion modes of operation. These studies show that a balance of net doping between that near the surface and that around the BC-layer is a stringent requirement for the Vt control in BC-pFETS.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122092385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A pipelined 14-tap parallel decision-feedback decoder for 1000BASE-T Gigabit Ethernet 用于1000BASE-T千兆以太网的流水线式14分路并行决策反馈解码器
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934497
E. Haratsch, K. Azadet
{"title":"A pipelined 14-tap parallel decision-feedback decoder for 1000BASE-T Gigabit Ethernet","authors":"E. Haratsch, K. Azadet","doi":"10.1109/VTSA.2001.934497","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934497","url":null,"abstract":"Parallel decision feedback decoding is the preferred algorithm for joint postcursor equalization and trellis decoding in 1000BASE-T Gigabit Ethernet, as it achieves most of the theoretically possible coding gain at a reasonable hardware complexity. However, the VLSI implementation of a 125 MHz, 14-tap parallel decision-feedback decoder (PDFD) is very challenging because of the critical path problem. This paper presents a pipelined 14-tap PDFD VLSI architecture for 1000BASE-T. The design is implemented in 3.3 V 0.16 /spl mu/m standard cell CMOS process and operates at 125 MHz to achieve 1 Gb/s throughput. Compared to a conventional 14-tap PDFD implementation, the processing speed is improved by a factor of two.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129633906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
PD/SOI CMOS Schmitt trigger circuits with controllable hysteresis 具有可控迟滞的PD/SOI CMOS施密特触发电路
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934540
J. Kuang, C. Chuang
{"title":"PD/SOI CMOS Schmitt trigger circuits with controllable hysteresis","authors":"J. Kuang, C. Chuang","doi":"10.1109/VTSA.2001.934540","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934540","url":null,"abstract":"This paper presents an SOI circuit technique, which eliminates the uncontrollable floating-body-induce hysteretic component in the transfer characteristics of CMOS Schmitt triggers. This technique integrates a successive switching threshold shift mechanism with the systematic body contact scheme. The resulting design possesses improved noise immunity and well-defined hysteresis behavior, suitable for use as a low-noise receiver, waveform-reshaping circuit, or delay element in VLSI applications.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"136 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130865297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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