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2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)最新文献

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High-speed, power-conscious circuit design techniques for high-performance computing 用于高性能计算的高速、节能电路设计技术
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934539
O. Takahashi, S. Dhong, P. Hofstee, J. Silbelman
{"title":"High-speed, power-conscious circuit design techniques for high-performance computing","authors":"O. Takahashi, S. Dhong, P. Hofstee, J. Silbelman","doi":"10.1109/VTSA.2001.934539","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934539","url":null,"abstract":"Future high-performance computing systems, including some of the embedded systems, require not just high-speed circuit design techniques, but also require power-conscious design, so that the whole system could be optimized for the highest performance achievable. A fresh look at high-speed circuits with power in mind is needed.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123172230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Algorithmic complexity, motion estimation and a VLSI architecture for MPEG-4 core profile video codecs 算法复杂性，运动估计和MPEG-4核心配置视频编解码器的VLSI架构
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934512
W. Stechele
{"title":"Algorithmic complexity, motion estimation and a VLSI architecture for MPEG-4 core profile video codecs","authors":"W. Stechele","doi":"10.1109/VTSA.2001.934512","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934512","url":null,"abstract":"A VLSI architecture with flexible, application-specific coprocessors for object based video encoding/decoding is presented. This architecture combines high performance of dedicated ASIC architectures with the flexibility of programmable processors. Dataflow and memory access were optimized based on extensive studies of statistical complexity variations. The architecture consists of a standard embedded core, as well as coprocessor modules for macroblock algorithms, motion estimation and bitstream processing. Results on silicon area and clock rate, required for realtime processing of MPEG-4 core profile video, are presented, as well as a comparison with software implementations on a standard RISC architecture.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"503 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123565733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A method of analysis of the F base strip process effect on the polycide film 一种分析F基带工艺对聚氰胺薄膜影响的方法
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934532
Pin-Yi Hsin, S. Kuo, Yu-Lun Lin
{"title":"A method of analysis of the F base strip process effect on the polycide film","authors":"Pin-Yi Hsin, S. Kuo, Yu-Lun Lin","doi":"10.1109/VTSA.2001.934532","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934532","url":null,"abstract":"In VLSI technology, photoresist is used as a mask for the pattern transfer by the etch processes, and also for the electrical regime defining processes performed by the ion implantation process. An oxygen plasma ashing process is usually implemented subsequently for the photoresist removal. In the ashing processes involving a high current/high dosage implantation process, a gas with extra F ions, like CF/sub 4/ and C/sub 2/F/sub 6/, needs to be added into the O/sub 2/ plasma to increase the strip ability. Among the F base gases, CF/sub 4/ is the most powerful gas. However, the addition of the fluorine based gases could damage the integrity of the exposed tungsten silicide layer, which is deposited on the top of the poly gate to reduce the polysilicon film contact resistance. In this paper, the addition of the CF/sub 4/ gas in the plasma ashing processes was studied for the effect on the WSix integrity. This study is done by collecting the correlation of loss rate on the WSix film and on the PE oxide film during the ashing processes containing the CF4 gas. The correlation is then reviewed with the final electrical data, and summarizes the fluorine ashing gas effect on the electrical outcomes. Through this study, the effect of the ashing processes on the device performance can be predicted before setting up the new ashing recipes for production.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125684906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure 5 GHz波段CMOS低噪声放大器，噪声系数为2.5 dB
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934525
Eric H. Westerwick
{"title":"A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure","authors":"Eric H. Westerwick","doi":"10.1109/VTSA.2001.934525","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934525","url":null,"abstract":"The noise performance of a radio receiver is largely determined by the noise figure of the first-stage amplifier. The amplifier also must have high gain and remain linear when presented with large input signals to minimize distortion in the receiver output. Amplifiers having high performance in the 5 GHz band are often composed of discrete components or integrated using GaAs or Si bipolar technologies. This work demonstrates a fully integrated high performance 5.25 GHz LNA realized with a 0.25 /spl mu/m linear CMOS technology.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132680084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
SOI technology for the GHz era 千兆赫时代的SOI技术
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934469
G. Shahidi
{"title":"SOI technology for the GHz era","authors":"G. Shahidi","doi":"10.1109/VTSA.2001.934469","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934469","url":null,"abstract":"Silicon on Insulator (SOI) CMOS offers 20-35% performance gain over bulk CMOS. High performance microprocessors using SOI CMOS have been shipping since 1998. As we move to 0.13 /spl mu/m generation, it will be used by more companies, and spread to lower-end microprocessors and SRAMs. In this paper, after a short history of SOI in IBM, we will describe causes of performance gain on SOI, and its scalability to 0.1 /spl mu/m generation and beyond. Some of the recent applications of SOI in high-end microprocessors will be described. It is fully expected that as we move to 0.1 /spl mu/m and beyond, SOI is the technology of choice for applications which require high performance, and/or low power.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130798295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 221
Stack capacitor integration with buried oxygen barrier using chemical mechanical polishing of noble metals 用化学机械抛光贵金属的埋氧屏障堆叠电容器集成
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934535
R. Schnabel, G. Beitel, P. Bosk, C. Dehm, A. Hauser, I. Kasko, G. Mainka, T. Mikolajick, H.D. Mullegger, N. Nagel, M. Rohner, S. Poppa, C. Sama, U. Scheler, V. Weinrich
{"title":"Stack capacitor integration with buried oxygen barrier using chemical mechanical polishing of noble metals","authors":"R. Schnabel, G. Beitel, P. Bosk, C. Dehm, A. Hauser, I. Kasko, G. Mainka, T. Mikolajick, H.D. Mullegger, N. Nagel, M. Rohner, S. Poppa, C. Sama, U. Scheler, V. Weinrich","doi":"10.1109/VTSA.2001.934535","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934535","url":null,"abstract":"A novel integration scheme for the formation of stack capacitor electrodes and diffusion barriers is presented. The concept makes use of chemical mechanical polishing of noble metals and allows the integration of a dielectric barrier. Electrical data is presented showing excellent parametric yield of contact resistance comparable to standard integration using RIE. Based on the data presented, a variety of new integration schemes for new materials can be deducted.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134158863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An efficient clock scheme for low-voltage four-phase charge pumps 低压四相电荷泵的有效时钟方案
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934526
Hongchin Lin, N. Chen
{"title":"An efficient clock scheme for low-voltage four-phase charge pumps","authors":"Hongchin Lin, N. Chen","doi":"10.1109/VTSA.2001.934526","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934526","url":null,"abstract":"A new four-phase clock scheme for the four-phase charge pumping circuits at very low supply voltages using 0.5 /spl mu/m double poly CMOS technology to generate high boosted voltages is presented. The boosted clocks are applied on the capacitors connected to the gates of the major pumping transistors. With the new clock generator, the charge pump can efficiently pump to 8 V using 10 stages at V/sub dd/=1 V by simulations and 4.7 V using 4 stages at V/sub dd/=1.5 V by measurements.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116935972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
New efficient low-complexity architecture for performing inversion and divisions 新的高效低复杂度架构，用于执行反转和除法
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934544
Chung-Hsin Liu
{"title":"New efficient low-complexity architecture for performing inversion and divisions","authors":"Chung-Hsin Liu","doi":"10.1109/VTSA.2001.934544","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934544","url":null,"abstract":"In this investigation based on an irreducible all-one polynomial (AOP), we present the proposed inner-product multiplication algorithm. The proposed architecture has a lower per cell circuit complexity and shorter computing delay time than conventional multipliers. Based on the algorithm, we construct the novel inverters and divisors of the cellular architecture. From the point of view of hardware implementation, a dedicated AB/sup 2/ circuit would be more effective both in constructing an architecture for inversion and division and in constructing an exponentiator in GF(2/sup m/).","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115178416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Joint activity for semiconductor R&D and role of Semiconductor Technology Academic Research Center (STARC) 半导体研发联合活动及半导体技术学术研究中心(STARC)的作用
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934468
T. Takemoto
{"title":"Joint activity for semiconductor R&D and role of Semiconductor Technology Academic Research Center (STARC)","authors":"T. Takemoto","doi":"10.1109/VTSA.2001.934468","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934468","url":null,"abstract":"Manufacturers are facing new issues in that circuit designs incorporating tens of millions of transistors must be completed in a short period of time. It will be difficult to overcome this issue using extensions of existing design technologies. STARC is thus promoting technological developments aimed at the resolution of this problem through a new approach, namely, the introduction of automation in the high-level design stages of system development, and reuse of design assets. STARC develops strategic IP design technologies, including technologies for reducing power consumption. STARC is also training LSI design engineers in companies, and providing educational support for semiconductor research at universities.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125798005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High quality factor silicon-integrated spiral inductors achieved by using thick top metal with different passivation schemes 采用不同钝化方案的厚顶金属实现了高质量因数的硅集成螺旋电感
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934506
S. Chu, K. Chew, W. Loh, Y.M. Wang, B.G. Onn, Y. Ju, J. Zhang, K. Shao
{"title":"High quality factor silicon-integrated spiral inductors achieved by using thick top metal with different passivation schemes","authors":"S. Chu, K. Chew, W. Loh, Y.M. Wang, B.G. Onn, Y. Ju, J. Zhang, K. Shao","doi":"10.1109/VTSA.2001.934506","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934506","url":null,"abstract":"A novel approach combining 2 /spl mu/m thick top metal, stacked design and different passivation schemes has been adopted to realize high quality factor (Q) inductors fabricated using a conventional 0.25 /spl mu/m 5-level metal CMOS technology. Q-factor enhancement of greater than 50% at 2.45 GHz has been achieved. It has been found that the passivation scheme utilizing 17 k/spl Aring/ of high density plasma (HDP) oxide is most effective in boosting the Q-factor. The above highlighted techniques can be easily implemented in any standard CMOS technology without additional increase in cost to the end-users.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121836808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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