Algorithmic complexity, motion estimation and a VLSI architecture for MPEG-4 core profile video codecs

A VLSI architecture with flexible, application-specific coprocessors for object based video encoding/decoding is presented. This architecture combines high performance of dedicated ASIC architectures with the flexibility of programmable processors. Dataflow and memory access were optimized based on extensive studies of statistical complexity variations. The architecture consists of a standard embedded core, as well as coprocessor modules for macroblock algorithms, motion estimation and bitstream processing. Results on silicon area and clock rate, required for realtime processing of MPEG-4 core profile video, are presented, as well as a comparison with software implementations on a standard RISC architecture.