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2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)最新文献

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A study of bimodal distributions of time-to-failure of copper via electromigration 铜电迁移失效时间的双峰分布研究
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934537
J. B. Lai, J.L. Yang, Y. Wang, S.H. Chang, R. Hwang, Y.S. Huang, C. Hou
{"title":"A study of bimodal distributions of time-to-failure of copper via electromigration","authors":"J. B. Lai, J.L. Yang, Y. Wang, S.H. Chang, R. Hwang, Y.S. Huang, C. Hou","doi":"10.1109/VTSA.2001.934537","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934537","url":null,"abstract":"Bimodal distributions of time-to-failure (TTF) were often seen in copper via electromigration (EM) tests. The failure mechanism of the stressed samples could be correlated to time-to-failure of the EM test. Early-failures were via-related, whereas late-failures were metal-stripe-related. The failure mechanisms are discussed.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132741325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Impact of 0.25 /spl mu/m dual gate oxide CMOS process on the flicker noise characteristics of multi-fingered MOSFETs for wireless applications 0.25 /spl μ m双栅氧化CMOS工艺对无线多指mosfet闪烁噪声特性的影响
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934524
K. Chew, K. S. Yeo, S. Chu, Y.M. Wang
{"title":"Impact of 0.25 /spl mu/m dual gate oxide CMOS process on the flicker noise characteristics of multi-fingered MOSFETs for wireless applications","authors":"K. Chew, K. S. Yeo, S. Chu, Y.M. Wang","doi":"10.1109/VTSA.2001.934524","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934524","url":null,"abstract":"The low frequency noise performance of 0.25 /spl mu/m thin-gate CMOS transistors from the dual gate oxide process and the standard single gate oxide process are evaluated and compared. The results reveal that thin-gate transistors from the dual gate oxide process show an order reduction in the current noise spectra. In general, the low frequency noise behaviour of the fabricated deep-submicrometer MOSFETs is best described by the number fluctuations with correlated mobility fluctuations model.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132562784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A programmable BIST for embedded SDRAM 嵌入式SDRAM的可编程BIST
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934530
M. Zhang, D. Tao, B. Wei
{"title":"A programmable BIST for embedded SDRAM","authors":"M. Zhang, D. Tao, B. Wei","doi":"10.1109/VTSA.2001.934530","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934530","url":null,"abstract":"The BIST (Built-In-Self-Test) provides a cost-effective solution in testing an embedded DRAM. This project develops a programmable BIST in support of a variety of test algorithms and SDRAM operation modes. The Verilog BIST modules are parameterized such that an SDRAM BIST circuit can be generated for a given SDRAM configuration. Also developed is software supporting mapping between physical and logical addresses and data, as well as translation from assembly programs to machine code used directly by the BIST. The result is an easy-to-use BIST generator for testing embedded SDRAMS.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133126178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Extraction of impurity concentration profiles by the DCIV method 用DCIV法提取杂质浓度谱
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934475
Yihui Wang, C. Sah
{"title":"Extraction of impurity concentration profiles by the DCIV method","authors":"Yihui Wang, C. Sah","doi":"10.1109/VTSA.2001.934475","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934475","url":null,"abstract":"The lineshape of the DCIV (Base Current vs Gate Voltage) characteristics is used to extract the spatial variation of the surface impurity concentration in the drain and source extension regions, the drain and source junction regions, and the basewell channel region. Examples are presented to illustrate nanometer spatial resolution of defect enhanced impurity diffusion, nitride barrier against boron penetration through thin gate oxide, and strain-induced interface traps.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128219821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The design of automatic-lock-automatic-retrieve single-chip IPM for converter systems 转换器系统的自动锁定自动检索单片机IPM的设计
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934528
L. Chang, M. Tsai
{"title":"The design of automatic-lock-automatic-retrieve single-chip IPM for converter systems","authors":"L. Chang, M. Tsai","doi":"10.1109/VTSA.2001.934528","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934528","url":null,"abstract":"This paper describes a single-chip intelligent power module (IPM) manufactured by utilizing a modified high voltage BCD process that integrates power devices, LIGBTs, and protection circuits on the SOI substrate. The smart integrated circuits provide automatic-lock-automatic-retrieve sensing and protection functions to give strong and fast protection ability against faults of over-on-state-voltage, over-current, and over-temperature; those are specially designed for power converter usage. When the gate voltage of LIGBT is high and the faulty event is sensed, the protection circuit pulls down the gate voltage to low and toggles LIGBT to off state immediately. However, each time the gate voltage returns to high, LIGBT is retrieved to the normal operating condition automatically. Therefore, the proposed IPM is superior to the converters with pulse-width-modulation (PWM) applications.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133478755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Highly integrated RF-ICs for digital cellular 2G and 3G and cordless systems-a status review and development trends 用于数字蜂窝2G和3G以及无线系统的高度集成射频集成电路——现状综述和发展趋势
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934498
J. Fenk
{"title":"Highly integrated RF-ICs for digital cellular 2G and 3G and cordless systems-a status review and development trends","authors":"J. Fenk","doi":"10.1109/VTSA.2001.934498","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934498","url":null,"abstract":"TDMA based digital systems like GSM for cellular and DECT for cordless application have created since 1992 an increasing market within Europe and gained widespread acceptance also outside Europe. In the meantime the cellular based 2G network is coming already in some megalopolis to its limit. The 3G WCDMA based UMTS systems will in future increase the available bandwith and throughput and enable further increased data service up to 2.048 Mbit. The author gives an overview of these systems. The system requirements and their influences on highly integrated RF ICs for GSM, DECT and UMTS are discussed. A brief overview about the technologies in use for these RF ICs is given. The various trends of progress in integration are shown, with the different advantages and disadvantages of the concepts in use. The challenges of increasing the level of integration and an outlook to the future is presented.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121977635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A high performance CMOS device with inverter delay 13 ps at 1.2 V power supply 一种高性能CMOS器件，在1.2 V电源下具有13 ps的逆变器延迟
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934509
T. P. Chen, S. Biesemans, Shui-Ming Cheng, J. Hong, Y. S. Huang, Yao-Ching Cheng, K. Holihan, L. K. Han, T. Schafbuer, C. Wann, Jenkon Chen
{"title":"A high performance CMOS device with inverter delay 13 ps at 1.2 V power supply","authors":"T. P. Chen, S. Biesemans, Shui-Ming Cheng, J. Hong, Y. S. Huang, Yao-Ching Cheng, K. Holihan, L. K. Han, T. Schafbuer, C. Wann, Jenkon Chen","doi":"10.1109/VTSA.2001.934509","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934509","url":null,"abstract":"A gate delay 13 ps operating at 1.2 V has been developed for 0.13 /spl mu/m CMOS logic technology application. In this work, the Leff of device is 0.08 um and the inversion oxide thickness is 3.2 nm. NMOS and PMOS transistor drive currents are 630 uA/um and 270 uA/um respectively at Ioff=4 nA/um. The Vt,sat rolloff from the nominal gate length to the worst gate length is about 50 mV for NMOS and 30 mV for PMOS.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122221867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Effect of enhanced nitridation in PECVD-Ti process for sub-0.2 /spl mu/m metal bit-line common contact process 在低于0.2 /spl mu/m的金属位线共接触工艺中强化氮化对PECVD-Ti工艺的影响
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934491
H. Park, K. Moon, M. Lee, S. Kang, G. Choi, Y. Park, J. Moon
{"title":"Effect of enhanced nitridation in PECVD-Ti process for sub-0.2 /spl mu/m metal bit-line common contact process","authors":"H. Park, K. Moon, M. Lee, S. Kang, G. Choi, Y. Park, J. Moon","doi":"10.1109/VTSA.2001.934491","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934491","url":null,"abstract":"The implementation of W bit-line enabled the integration of n+ and p+ common contact process at bit-line level. Despite the advantages of the common contact process such as chip-area reduction and elimination of the burden associated with MC dry etch, the immediate implementation of the common contact is difficult due to large increase of p+ contact resistance with high thermal budget capacitor process. The results of the present investigation indicate that the thickness of TiSi/sub 2/ layer must be minimized in order to prevent the out-diffusion of boron into silicide layer. However, simply reducing the thickness of TiSi/sub 2/ presents another problem since it leads to a discontinuous layer of TiSi/sub 2/. Heavily increasing the dosage of p+ plug implantation, which is another way of preventing the depletion of boron dopants, resulted in degradation of p+ contact resistance. Therefore, the dopant out-diffusion alone cannot explain the degradation of p+ contact resistance. In order to minimized the thickness of TiSi/sub 2/, enhanced nitridation after deposition of PECVD-Ti was tested and resulted in effective reduction of the p+ contact resistance by 25%. The TEM and SIMS analysis showed that the additional growth of TiSi/sub 2/ during high thermal budget post annealing was suppressed by the enhanced nitridation. The mechanism responsible for reducing the p+ contact resistance by the enhanced nitridation is attributed to the prevention of the dopant depletion at the interface between TiSi/sub 2/ and Si due to the suppressed formation of additional TiSi/sub 2/.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124777560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
New experimental evidences of the plasma charging enhanced hot carrier effect and its impact on surface channel CMOS devices 等离子体充电增强热载子效应及其对表面通道CMOS器件影响的新实验证据
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934476
Sz-Hau Chen, C. -. Lin, S. Chung, H. Lin
{"title":"New experimental evidences of the plasma charging enhanced hot carrier effect and its impact on surface channel CMOS devices","authors":"Sz-Hau Chen, C. -. Lin, S. Chung, H. Lin","doi":"10.1109/VTSA.2001.934476","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934476","url":null,"abstract":"Plasma etching of polysilicon gate in CMOS devices induces plasma edge damage. This damage will be enhanced in the successive plasma processes. New experimental evidences of this effect is examined in this study. Results have been verified for both surface channel n- and p-MOSFETs. First, from the measurements of high-density antenna structures, this enhanced edge damage has been characterized by the charge-pumping profiling technique. Then, a 4-phase edge damage mechanism has been proposed. For the first time, it was found that a two-peak spatial distribution of the interface state was found near the device drain region. We call it Plasma Charging Enhanced Hot Carrier (PCE-HC) effect. This enhanced damage effect will induce further device degradation, in particular for the scaled devices.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125408929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Isothermal wafer-level electromigration test for the characterization of metal system reliability monitoring 等温晶圆级电迁移试验表征金属系统可靠性监测
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934538
C. Kuo, H. Yuan, S.C. Lee, S.Y. Lee, L. Chu, R. Shiue, J. Yue
{"title":"Isothermal wafer-level electromigration test for the characterization of metal system reliability monitoring","authors":"C. Kuo, H. Yuan, S.C. Lee, S.Y. Lee, L. Chu, R. Shiue, J. Yue","doi":"10.1109/VTSA.2001.934538","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934538","url":null,"abstract":"A fast isothermal wafer-level electromigration method has been demonstrated to evaluate interconnect metal line performance. The stress current is increased quickly until the metal line temperature reached the stress target temperature. This test method offers a significant short test time and rapid feedback to bring reliability issues into the development process. Interconnect metal lines with width/thickness of 0.9 /spl mu/m/4000 /spl Aring/ and 1.2 /spl mu/m/8000 /spl Aring/ of this study were processed and stressed. Results show that the metal line mean-time-to-failure and resistance are affected when the dimension is lost. This isothermal electromigration test methodology is therefore shown to be a useful tool for process monitoring.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129219255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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