一种高性能CMOS器件，在1.2 V电源下具有13 ps的逆变器延迟

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI:10.1109/VTSA.2001.934509

T. P. Chen, S. Biesemans, Shui-Ming Cheng, J. Hong, Y. S. Huang, Yao-Ching Cheng, K. Holihan, L. K. Han, T. Schafbuer, C. Wann, Jenkon Chen

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引用次数: 1

摘要

针对0.13 /spl mu/m CMOS逻辑技术应用，开发了一种工作在1.2 V下的栅极延迟13ps。在本工作中，器件的左距为0.08 um，反转氧化物厚度为3.2 nm。在Ioff=4 nA/um时，NMOS和PMOS晶体管驱动电流分别为630 uA/um和270 uA/um。从标称栅极长度到最差栅极长度的Vt,sat滚降对于NMOS约为50 mV，对于PMOS约为30 mV。

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A high performance CMOS device with inverter delay 13 ps at 1.2 V power supply

A gate delay 13 ps operating at 1.2 V has been developed for 0.13 /spl mu/m CMOS logic technology application. In this work, the Leff of device is 0.08 um and the inversion oxide thickness is 3.2 nm. NMOS and PMOS transistor drive currents are 630 uA/um and 270 uA/um respectively at Ioff=4 nA/um. The Vt,sat rolloff from the nominal gate length to the worst gate length is about 50 mV for NMOS and 30 mV for PMOS.

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2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

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