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2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)最新文献

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Design and implementation of a bitstream parsing coprocessor for MPEG-4 video system-on-chip solution 用于MPEG-4视频片上系统解决方案的位流解析协处理器的设计与实现
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934516
Yung-Chi Chang, Rlao-Chieh Chang, Liang-Gee Chen
{"title":"Design and implementation of a bitstream parsing coprocessor for MPEG-4 video system-on-chip solution","authors":"Yung-Chi Chang, Rlao-Chieh Chang, Liang-Gee Chen","doi":"10.1109/VTSA.2001.934516","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934516","url":null,"abstract":"In this paper, the hardware-oriented bitstream structure analysis and an efficient and flexible bitstream parsing processor are presented. The analysis of MPEG-4 video bitstream structure based on RISC model explores requirement and design constraint for bitstream-level processing. It shows that conventional RISC is not efficient enough for bitstream parsing. An efficient instruction set optimized for bitstream processing is designed and the hardware architecture can be reconfigured for various applications. Compared with 160 MOPS required by a RISC, the proposed architecture needs only about 27 MOPS to parse an MPEG-4 video bitstream at high bit-rate as about 40 Mbit/s, which is about 6 times speedup. The impact of the proposed architecture on video applications is to enhance and extend the processing for bit domain translation and related real time applications.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132571374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Effects of polysilicon shield on spiral inductors for silicon-based RF IC's 多晶硅屏蔽对硅基射频集成电路中螺旋电感的影响
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934507
C. Sia, K. S. Yeo, W. Goh, T. N. Swe, C. Y. Ng, K. Chew, W. Loh, S. Chu, L. Chan
{"title":"Effects of polysilicon shield on spiral inductors for silicon-based RF IC's","authors":"C. Sia, K. S. Yeo, W. Goh, T. N. Swe, C. Y. Ng, K. Chew, W. Loh, S. Chu, L. Chan","doi":"10.1109/VTSA.2001.934507","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934507","url":null,"abstract":"Increasing demands for more affordable personal mobile communication equipment have motivated research and development of low cost, high performance silicon-based on-chip inductors. Current silicon technology uses a conductive substrate, which causes unwanted energy dissipation. Inserting a patterned polysilicon shield beneath inductors can help reduce this substrate loss. Effects of the polysilicon ground shield on inductor performance have been investigated. An inductor utilizing a new high resistivity polysilicon floating shield is shown in this paper to have improved inductive characteristics.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130906272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
New stack gate insulator structure strongly reduces FIBL effect 新型叠栅绝缘子结构有力地降低了FIBL效应
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934523
Cheng-Hsiao Lai, Ling-Chang Hu, Hai-Ming Lee, Long-Je Do, Y. King
{"title":"New stack gate insulator structure strongly reduces FIBL effect","authors":"Cheng-Hsiao Lai, Ling-Chang Hu, Hai-Ming Lee, Long-Je Do, Y. King","doi":"10.1109/VTSA.2001.934523","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934523","url":null,"abstract":"Recent studies have shown that by adapting high-k gate dielectric, deep sub-micron MOSFET suffers short channel effect caused by the fringing electric fields from gate to source/drain regions. In this work, a simulation-based analysis of multiple gate stack structure with channel length as low as 50 nm is presented. The new stack gate structure can be optimized for reducing the undesirable fringing induced barrier lowering effect of a high-k gate dielectric device.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123826683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of k-WTA/Sorting network using maskable WTA/MAX circuit 利用可屏蔽WTA/MAX电路设计k-WTA/排序网络
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934485
Chi-Sheng Lin, S. Ou, Bin-Da Liu
{"title":"Design of k-WTA/Sorting network using maskable WTA/MAX circuit","authors":"Chi-Sheng Lin, S. Ou, Bin-Da Liu","doi":"10.1109/VTSA.2001.934485","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934485","url":null,"abstract":"This paper presents a novel circuit for the k-WTA/Sorting network that processes eight 8-bit patterns. This design is based on a maskable WTA/MAX circuit which generates maximum value and winner with maskable skill. It can obtain the whole system functions: WTA/MAX/k-WTA/Sorter without adding any extra components. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The chip was fabricated with the TSMC 0.35/spl square/m SPQM CMOS process. Experimental results indicate this chip can work up to 66 MHz with power consumption less than 10 mW at 3.3 V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126637597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
DSP implementation issues in 1000BASE-T Gigabit Ethernet 1000BASE-T千兆以太网中DSP实现问题
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934495
K. Azadet, E. Haratsch
{"title":"DSP implementation issues in 1000BASE-T Gigabit Ethernet","authors":"K. Azadet, E. Haratsch","doi":"10.1109/VTSA.2001.934495","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934495","url":null,"abstract":"This is the second part of a tutorial on 1000BASE-T, physical layer of Gigabit Ethernet over copper. A general presentation of the 1000BASE-T standard was given in a previous communication [Azadet, 1999]. In this paper we focus on one of the main challenges in Gigabit Ethernet: DSP implementation. After presenting a reference implementation of the receiver we describe low-power digital adaptive filter architectures, and techniques for combining Viterbi and Decision Feedback Equalizers (DFE). The last section studies the critical path and complexity of the joint Viterbi/DFE decoder.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126790134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Demonstration of a flash memory cell with 55 /spl Aring/ EOT silicon nitride tunnel dielectric 具有55 /spl Aring/ EOT氮化硅隧道介质的快闪存储单元的演示
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934502
A. Melik-Martirosian, T. Ma, X.W. Wang, X. Guo, F. Widdershoven, D. Wolters, V.J.D. van der Wal, M. van Duuren
{"title":"Demonstration of a flash memory cell with 55 /spl Aring/ EOT silicon nitride tunnel dielectric","authors":"A. Melik-Martirosian, T. Ma, X.W. Wang, X. Guo, F. Widdershoven, D. Wolters, V.J.D. van der Wal, M. van Duuren","doi":"10.1109/VTSA.2001.934502","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934502","url":null,"abstract":"The authors demonstrate for the first time a flash memory cell with 55 /spl Aring/ Equivalent Oxide Thickness (EOT) silicon nitride tunnel dielectric. Their preliminary results show that this cell has good endurance characteristics and high program/erase speed. These results suggest that a high-quality JVD silicon nitride can be used as a long term solution to replace the tunnel oxide and to extend the scaling limit of tunnel dielectric in flash memory devices beyond the year 2010.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128464083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Level shifters for high-speed 1 V to 3.3 V interfaces in a 0.13 /spl mu/m Cu-interconnection/low-k CMOS technology 用于高速1v至3.3 V接口的电平转换器，采用0.13 /spl mu/m cu互连/低k CMOS技术
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934546
Wen-Tai Wang, M. Ker, M. Chiang, Chung-Hui Chen
{"title":"Level shifters for high-speed 1 V to 3.3 V interfaces in a 0.13 /spl mu/m Cu-interconnection/low-k CMOS technology","authors":"Wen-Tai Wang, M. Ker, M. Chiang, Chung-Hui Chen","doi":"10.1109/VTSA.2001.934546","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934546","url":null,"abstract":"Level shifters for 1.0 V to 3.3 V high-speed interfaces are proposed. Level-up shifter uses zero-Vt 3.3 V NMOSs as voltage clamps to protect 1.0 V NMOS switches from high voltage stress across the gate oxide. Level-down shifter uses 3.3 V NMOSs as both pull-up and pull-down devices with supply voltage of 1.0 V and gate voltage swing from 0 V to 3.3 V. The zero-Vt NMOS is a standard MOSFET device in a 0.13 /spl mu/m CMOS process without adding extra mask or process step to realize it. Level-up transition from 0.9 V to 3.6 V takes only 1 ns in time, and the level-down transition has no minimum core voltage limitation. These circuits do not consume static DC power, therefore they are very suitable for low-power and high-speed interfaces in the deep sub-quarter-micron CMOS technologies.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131707174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Fast placement-dependent full chip thermal simulation 快速位置相关的全芯片热模拟
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934531
Zhiping Yu, D. Yergeau, R. Dutton, S. Nakagawa, J. Deeney
{"title":"Fast placement-dependent full chip thermal simulation","authors":"Zhiping Yu, D. Yergeau, R. Dutton, S. Nakagawa, J. Deeney","doi":"10.1109/VTSA.2001.934531","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934531","url":null,"abstract":"A general purpose semiconductor device/process simulator, PROPHET, has been adapted for full chip thermal analysis and is capable of quickly (/spl sim/1 minute CPU time) assessing the impact of functional block placement on chip temperature distribution. The key to fast simulation is a new algorithm which maps the heat generation of functional blocks to a coarse mesh while maintaining conservation of heat generating sources. Design of two high-performance CPU chips based on bulk CMOS and SOI technologies, with total power consumption of 100 and 60 watts, respectively, has been evaluated for thermal performance using this approach. Excellent results have been achieved in terms of benchmarked accuracy and computational efficiency. Up to seven interconnect layers have been included in the simulation; effects of packaging are modeled using two capping thermally resistive layers on top and bottom of the chip. Considering the extremely non-uniform nature of interconnect/interleaving-insulating layers, anisotropic thermal conductivity is a critical factor in modeling thermal properties and has been implemented in the simulator. The potential benefit of using pure silicon (Si-28), which has a higher thermal conductivity than that of natural silicon (1.6 times as big at the room temperature), in reducing the peak chip temperature has also been studied. It is shown that with a power consumption level of 100 watts, the peak temperature can be lowered by about 10% (from 136 to 123/spl deg/C).","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115382501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
An analog and digital record, playback and processing system using a coarse-fine programming method 一种采用粗-精编程方法的模拟和数字记录、回放和处理系统
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934517
P. Holzmann, G. Jackson, A. Raina, Hung-Chuan Pai, Ming-Bing Chang, S. Awsare, L. Engh, O. C. Kao, C. R. Palmer, Chun-Mai Liu, A.V. Kordesch, K. Su, M. Hemming
{"title":"An analog and digital record, playback and processing system using a coarse-fine programming method","authors":"P. Holzmann, G. Jackson, A. Raina, Hung-Chuan Pai, Ming-Bing Chang, S. Awsare, L. Engh, O. C. Kao, C. R. Palmer, Chun-Mai Liu, A.V. Kordesch, K. Su, M. Hemming","doi":"10.1109/VTSA.2001.934517","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934517","url":null,"abstract":"A system on chip for conditioning of voiceband analog audio signals and nonvolatile storage for use in mobile communication devices is presented. The system allows for direct interface to acoustic transducer elements and provides signal conditioning to gain adjust, multiplex, filter and mix two independent signals. The system can record these processed signals as analog samples in a nonvolatile flash EEPROM array for later retrieval. Together with the integrated signal path the system can store up to 16 minutes of audio signal. Control of the system is achieved via a serial interface, which is used to configure and control the device. The serial interface can also be used to store digital data into the flash EEPROM array. All necessary components of the system are provided on chip including analog processing elements, nonvolatile storage and high voltage and reference generation.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124277603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low temperature capacitor technology for embedded DRAM 嵌入式DRAM低温电容器技术
2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934494
C. Lo, C. Yu, W. Chien, C.H.J. Huang
{"title":"Low temperature capacitor technology for embedded DRAM","authors":"C. Lo, C. Yu, W. Chien, C.H.J. Huang","doi":"10.1109/VTSA.2001.934494","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934494","url":null,"abstract":"The experiments show that in the application of embedded DRAM, any post salicide process with temperature higher than 750/spl deg/C would degrade the electrical performance of salicide, especially the P/sup +/ poly Rs. The novel capacitor dielectric stack film (nitride/capping HTO) is proved acceptable in view of leakage current density, Vbd and TDDB reliability below 700/spl deg/C.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125212268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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