嵌入式DRAM低温电容器技术

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI:10.1109/VTSA.2001.934494

C. Lo, C. Yu, W. Chien, C.H.J. Huang

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引用次数: 0

摘要

实验表明，在嵌入式DRAM的应用中，任何温度高于750/spl℃的盐化后工艺都会降低盐化后的电性能，特别是P/sup +/ poly Rs。从泄漏电流密度、Vbd和TDDB可靠性来看，新型电容器介电堆膜(氮化/封盖HTO)在700/spl℃以下是可以接受的。

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Low temperature capacitor technology for embedded DRAM

The experiments show that in the application of embedded DRAM, any post salicide process with temperature higher than 750/spl deg/C would degrade the electrical performance of salicide, especially the P/sup +/ poly Rs. The novel capacitor dielectric stack film (nitride/capping HTO) is proved acceptable in view of leakage current density, Vbd and TDDB reliability below 700/spl deg/C.

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2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

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