Low temperature capacitor technology for embedded DRAM

Abstract

The experiments show that in the application of embedded DRAM, any post salicide process with temperature higher than 750/spl deg/C would degrade the electrical performance of salicide, especially the P/sup +/ poly Rs. The novel capacitor dielectric stack film (nitride/capping HTO) is proved acceptable in view of leakage current density, Vbd and TDDB reliability below 700/spl deg/C.