{"title":"Early-late gate receiving for Bluetooth packet","authors":"C. Peng, Ming-Hung Chang, K. Wen","doi":"10.1109/VTSA.2001.934482","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934482","url":null,"abstract":"An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of an Analog-to-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116966561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A cost effective binary FSK demodulator for low-IF radios","authors":"Kuang-Hu Huang, Chorng-Kuang Wang","doi":"10.1109/VTSA.2001.934501","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934501","url":null,"abstract":"This paper presents a design of low-cost continuous-phase binary frequency-shift keying (CP-BFSK) demodulator. The proposed demodulator does not require a post-detection filter to suppress sum-frequency components, and hence is suitable for a low-IF receiver architecture. Applied to a Bluetooth receiver with 500 kHz low-IF frequency, the demodulator reaches 10/sup -3/ BER for 16.5 dB SNR and 1 Mbps data-rate. Small modulation indices between 0.28 to 0.35 are demonstrated. Using a 0.25-/spl mu/m mixed-signal CMOS process, the demodulator occupies an active area of 0.22 mm/sup 2/. The power consumption is 5 mW from a 2.5 V single supply.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126551139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Hobbs, L. Dip, K. Reid, D. Gilmer, R. Hegde, T. Ma, B. Taylor, B. Cheng, S. Samavedam, H. Tseng, D. Weddington, F. Huang, D. Farber, M. Schippers, M. Rendon, L. Prabhu, R. Rai, S. Bagchi, J. Conner, S. Backer, F. Dumbuya, J. Locke, D. Workman, P. Tobin
{"title":"Sub-quarter micron Si-gate CMOS with ZrO/sub 2/ gate dielectric","authors":"C. Hobbs, L. Dip, K. Reid, D. Gilmer, R. Hegde, T. Ma, B. Taylor, B. Cheng, S. Samavedam, H. Tseng, D. Weddington, F. Huang, D. Farber, M. Schippers, M. Rendon, L. Prabhu, R. Rai, S. Bagchi, J. Conner, S. Backer, F. Dumbuya, J. Locke, D. Workman, P. Tobin","doi":"10.1109/VTSA.2001.934520","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934520","url":null,"abstract":"MOSFETs with a zirconium dioxide (ZrO/sub 2/) gate dielectric and poly-silicon gate were fabricated using a low temperature CMOS process. Well-behaved transistor characteristics were obtained for devices with sizes of 14 /spl mu/m/spl times/1.4 /spl mu/m or smaller. Devices 14 /spl mu/m/spl times/14 /spl mu/m or larger were found to be nonfunctional due to the formation of Zr-silicide at the polySi-gate/Zr0/sub 2/ interface. In this paper, we present results on the electrical and physical characterization.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127707013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 200 MHz analogue-ROM based direct digital frequency synthesiser with amplitude modulation","authors":"Sunay, Shah, S. Collins","doi":"10.1109/VTSA.2001.934481","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934481","url":null,"abstract":"A novel, low power frequency synthesiser system with 60 MHz output bandwidth is reported which is suitable for integration in a single chip RF transceiver. The system is based upon a conventional DDFS architecture. However, the problems which usually arise from the non-ideal behaviour of the DAC and the high power consumption of a ROM are avoided by using a non-volatile analogue memory array. Simulation results are presented which show that the system is suitable for use in an RF transceiver.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134210421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A low power FIR filter design technique using dynamic reduced signal representation","authors":"Zhan Yu, Meng-Lin Yu, K. Azadet, A. Willson","doi":"10.1109/VTSA.2001.934496","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934496","url":null,"abstract":"While arithmetic circuits using 2's complement representation are easy to implement, it is well-known that the sign-extension bits of a 2's complement number cause high switching activity in digital arithmetic circuits. Such switching is undesirable in low power applications. In this work, we exploit the sign-extension property of a 2's complement number and propose a reduced representation of 2's complement numbers to avoid sign-extension. Instead of having the high switching activity at the MSB side of the datapath, the proposed number representation avoids switching of the MSBs altogether, and therefore reduces the power dissipation in digital arithmetic circuits. With the proposed technique, the maximum magnitude of a 2's complement number is detected and a reduced representation is dynamically generated to represent the signal. There is a constant error introduced by the reduced representation and such error is compensated accordingly. The proposed signal representation is particularly useful in digital filters where the coefficients are slowly varying and have small magnitudes. Our experimental results have shown a 38% power saving using the proposed technique.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114095375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Youngsik Kim, Young-Wan Kim, Soon-jae Won, Jae-Shin Lee, Dae-Bong Choi, Won-Tae Kim, Taehack Lee, Tae-Yong Kim
{"title":"A system manager for network system-on-a-chip designs with various memory access types","authors":"Youngsik Kim, Young-Wan Kim, Soon-jae Won, Jae-Shin Lee, Dae-Bong Choi, Won-Tae Kim, Taehack Lee, Tae-Yong Kim","doi":"10.1109/VTSA.2001.934513","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934513","url":null,"abstract":"System-on-a-chip designs need to support various memory access types, such as a single transfer and a burst transfer with different transfer sizes, different access lengths, and both types of endian. This paper presents Samsung's S3C4520X which is the system-on-a-chip design for network applications with the system manager to efficiently support various memory access types. Also, the system manager is evaluated by analytical model in terms of memory access time.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124856508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Baroncini, P. Placidi, A. Scorzoni, G. Cardinali, L. Dori, S. Nicoletti
{"title":"Characterization of an embedded micro-heater for gas sensors applications","authors":"M. Baroncini, P. Placidi, A. Scorzoni, G. Cardinali, L. Dori, S. Nicoletti","doi":"10.1109/VTSA.2001.934510","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934510","url":null,"abstract":"The heating characteristic of a microheater element, plated onto a thermally insulated dielectric membrane, define the sensitivity and selectivity of a micromachined gas sensor. Therefore an accurate determination of its temperature is required. In this paper, we describe a new four-point probe heating element configuration together with a simple analytical model of its thermal behavior.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122409941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yujun Li, J. Sim, J. Mandelman, K. McStay, Q. Ye, G. Bronner
{"title":"Array transistor design challenges in trench capacitor DRAM technology","authors":"Yujun Li, J. Sim, J. Mandelman, K. McStay, Q. Ye, G. Bronner","doi":"10.1109/VTSA.2001.934489","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934489","url":null,"abstract":"BuriEd Strap Trench (BEST) array cell design has been extended for more than 4 generations. However, significant scaling challenges in planar trench DRAM technology will be encountered below the 0.1 /spl mu/m generation. In this paper, we review the key factors that limit the scaling of the BEST array cell, further analyze the scaling challenges considering design for manufacturability, and finally discuss other design and/or technology innovations including the vertical array transistor to overcome scaling limitations.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123809741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Luo, T. Ma, E. Cartier, M. Copel, T. Tamagawa, B. Halpern
{"title":"Thermally stable ultra-thin Zr silicate for CMOS applications","authors":"Z. Luo, T. Ma, E. Cartier, M. Copel, T. Tamagawa, B. Halpern","doi":"10.1109/VTSA.2001.934519","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934519","url":null,"abstract":"With the dramatic scaling of CMOS devices, numerous metal oxides and silicates with high dielectric constants are being pursued intensely to replace conventional SiO/sub 2/ as gate dielectrics. Among them, ZrO/sub 2/ and its silicates are considered to be the most promising candidates. In this study, we report on the electrical and physical properties of ultra-thin Zr Silicate/ZrO/sub 2/ films deposited by the jet-vapor-deposition (JVD) process. It is shown that films with equivalent oxide thickness (EOT) of 1 nm, with high thermal stability, low leakage and good electrical properties can be fabricated. Our analysis also shows that the compositions of JVD films vary with the thickness. Thinner films are found to be Zr-silicate-like, whereas thicker films appear to be graded with a transition to stoichiometric ZrO/sub 2/. The presence of a Zr silicate interfacial layer may prevent the formation of interfacial SiO/sub 2/, despite the fact that as-deposited films are found to be oxygen rich. In contrast to other ZrO/sub 2/ films reported in the literature, the EOTs of our films decrease after post deposition annealing. Another remarkable observation is that the JVD Zr silicate film can survive an annealing temperature as high as 1000/spl deg/C, suggesting that it can be used in a conventional CMOS process without the need for a replacement gate process.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134325275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance analysis of tapered gate in PD/SOI CMOS technology","authors":"W. Hwang, C. Chuang, B. Curran, M. Rosenfield","doi":"10.1080/00207210210127645","DOIUrl":"https://doi.org/10.1080/00207210210127645","url":null,"abstract":"\"Tapered gate\" is a device sizing methodology to improve the performance of critical paths in stacked circuit configurations. This paper presents a detailed study on the performance leverage of \"taped gate\" in a partially-depleted silicon-on-insulator (PD/SOI) technology. It is shown that because the reduced junction capacitance in the PD/SOI device renders the series resistance reduction of the lower transistors in the stack more effective, a \"tapered gate\" in PD/SOI technology has slightly larger improvement in the rising-input delays for the higher pins and slightly larger degradation on the lower pin falling-input delays compared with bulk CMOS technology. The effects are also shown to be more pronounced for low-V/sub T/ cases. The study demonstrates that \"tapered\" gate remains a viable device sizing technique/methodology for performance improvement in a PD/SOI technology.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130510532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}