2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)最新文献_第6页

A study on the effectiveness of different cap oxides for preventing fluorine out-diffusion from FSG 不同氧化帽防止氟从烟气中逸出的效果研究

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934533

P. Chou, Y.L. Cheng

{"title":"A study on the effectiveness of different cap oxides for preventing fluorine out-diffusion from FSG","authors":"P. Chou, Y.L. Cheng","doi":"10.1109/VTSA.2001.934533","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934533","url":null,"abstract":"In this paper, we investigate the effect of fluorine out-diffusion from fluorinated-silicate-glass (FSG) film stacks. The FSG film stack consists of 2 k/spl Aring/ cap oxide/6 k/spl Aring/ FSG/2 k/spl Aring/ liner oxide. Different cap oxide and liner oxide materials were studied in this work. The samples were annealed at 410/spl deg/C for several hours to simulate the various backend annealing processes. SIMS was used to measure the F distribution in the FSG film stack. We found that silicon nitride (SiNx) could effectively inhibit F diffusion from the FSG film. But this film stack was not stable under ion beam and electron beam irradiation. Plasma-Enhanced (PE) oxide cap on FSG film could not inhibit F diffusion from the FSG film very well, but it was stable under SIMS ion beam and electron beam irradiation. We also found that silicon rich oxide (SRO) inhibited F out-diffusion, and that the film stack was stable during SIMS analysis. Why does SRO inhibit F out-diffusion? From the SIMS results, we found N in the SRO film. Furthermore, the higher the concentration of N in the SRO film, the less the F diffused out. A series of experiments were carried out to study the effect of introducing nitrogen in both SRO and FSG in preventing F out-diffusion from FSG.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122991738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

The simple link protocol: a zero-overhead packet delineation scheme for high-speed Ethernet 简单链路协议:用于高速以太网的零开销包描绘方案

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934484

T. Truman, Leilei Song, K. Azadet

引用次数: 2

Nitride framed shallow trench isolation (NFSTI) for self-aligned buried strap in high performance trench capacitor DRAM/eDRAM 用于高性能沟槽电容DRAM/eDRAM自对准埋带的氮化框架浅沟槽隔离(NFSTI)

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934490

B. Kim, Y. Fukuzaki, G. K. Worth, J. Nuetzel, G. Williams, B. Lee, Y. Takegawa, S. Halle, T. Rupp, A. Sudo, R. Divakaruni, R. Srinivasan, T. Mii, G. Bronner

{"title":"Nitride framed shallow trench isolation (NFSTI) for self-aligned buried strap in high performance trench capacitor DRAM/eDRAM","authors":"B. Kim, Y. Fukuzaki, G. K. Worth, J. Nuetzel, G. Williams, B. Lee, Y. Takegawa, S. Halle, T. Rupp, A. Sudo, R. Divakaruni, R. Srinivasan, T. Mii, G. Bronner","doi":"10.1109/VTSA.2001.934490","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934490","url":null,"abstract":"A self-aligned buried strap process is developed, using nitride frame with oxide hard mask in shallow trench isolation (STI). The connection between cell access transistor and storage node electrode is a key process in trench type DRAM fabrication. Typical trench cell capacitor DRAM technology forms the strap connection under Si substrate (Buried Strap) for better surface planarity. Trench based e-DRAM has significant advantages due to wafer planarity. As the ground rule shrinks beyond 150 nm, the strap resistance variation is critical due to the overlay sensitivity. A new overlay independent strap formation method is introduced, using nitride framed self-aligned trench isolation process which eliminates any possible parasitic connection between the strap and substrate. Masking material and Si RIE process used in NFSTI formation improves array device characteristics. In addition, NFSTI process improves trench level alignment signal contrast due to a phase shift effect.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125442991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis and architecture design of lifting based DWT and EBCOT for JPEG 2000 jpeg2000下基于DWT和EBCOT的提升分析与体系结构设计

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934514

Chung-Jr Lian, Kuanfu Chen, Hong-Hui Chen, Liang-Gee Chen

引用次数: 17

CCD or CMOS image sensors for consumer digital still photography? CCD或CMOS图像传感器用于消费数码静态摄影?

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934511

A. Theuwissen

引用次数: 29

CAD infrastructure for high performance design 用于高性能设计的CAD基础设施

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934543

W. Vercruysse

引用次数: 0

Investigation of sputtered TaC/sub x/ and WC/sub x/ films as diffusion barriers for Cu metallization 溅射TaC/sub x/和WC/sub x/薄膜作为Cu金属化扩散屏障的研究

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934536

H. Tsai, Shui-Jinn Wang, S.C. Sun

引用次数: 0

Integration of CVD W on MOCVD TiN CVD W与MOCVD TiN的集成

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934534

C. Yu, M.Y. Wang, S. Shue, C. Yu, M. Liang

引用次数: 1

Novel implementation of 6th order MASH delta-sigma modulators for wideband and multi-standard applications 六阶MASH delta-sigma调制器的新实现，适用于宽带和多标准应用

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934500

K.T. Tiew, A. Payne, P. Cheung

引用次数: 8

A programming method for multilevel analog flash memory using coarse and fine sequence 一种基于粗、细序列的多电平模拟闪存编程方法

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934504

A. Kordesch, S. Awsare, J. Brennan, P. Guo, M. Hemming, P. Holzmann, Chun-Mai Liu, K. Su

引用次数: 4