2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)最新文献_第7页

Silicon RFIC's for a DCS1800 base station receiver downconverter 用于DCS1800基站接收机下变频器的硅RFIC

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934487

O. Boric-Lubecke, Jenshan Lin, P. Gould, C. Zelley, R. Yan

引用次数: 0

Architectures for network processing 网络处理体系结构

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934483

J. Williams

引用次数: 18

Tailoring logic CMOS for RF applications 用于射频应用的裁剪逻辑CMOS

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934505

J. Burghartz

引用次数: 5

Ultra shallow junction doping technology for sub-100 nm CMOS 亚100纳米CMOS的超浅结掺杂技术

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934474

B. Mizuno

引用次数: 0

Using syndrome compression for memory built-in self-diagnosis 利用综合征压缩进行记忆内置自诊断

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934545

Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu

引用次数: 11

Homogeneous multiprocessing and the future of silicon design paradigms 同质多处理和硅设计范例的未来

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934515

P. Stravers, J. Hoogerbrugge

{"title":"Homogeneous multiprocessing and the future of silicon design paradigms","authors":"P. Stravers, J. Hoogerbrugge","doi":"10.1109/VTSA.2001.934515","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934515","url":null,"abstract":"This paper addresses two challenges of the consumer semiconductor industry: (1) economical and social forces are increasingly reducing the length of product life cycles, and (2) the continuing exponential growth of the on-chip transistor count is pushing design complexity. In concert these two trends represent a formidable challenge for semiconductor companies that aim to benefit from future technological developments in highly competitive markets. The paper derives a relation between on-chip memory real estate and compute logic, suggesting that homogeneous multiprocessors are an unavoidable consequence of the technology curve. A particular approach to homogeneous multiprocessing is then presented that combines scalability with high computational performance and with high power efficiency. We also present the implementation of a programming paradigm for homogeneous multiprocessors that focuses on reuse of tested and approved functions at the software level. This enables a shift from today's not-so-successful practice of hardware core reuse to the reuse of functions that have very well defined and uniform interfaces. The time frame for large scale commercial application of this type of homogeneous multiprocessor architecture is expected to coincide with the arrival of 0.07 micron technology for consumer products, i.e. 2006 and beyond. The paper concludes with a case study of an MPEG2 decoder and how a few simple guidelines can significantly increase the exposed concurrency of the application.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116983538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 68

Device equivalence of logic performance in 0.18 /spl mu/m and extension to 0.13 /spl mu/m embedded DRAM technology 器件等效的逻辑性能在0.18 /spl mu/m和扩展到0.13 /spl mu/m嵌入式DRAM技术

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934493

S. Chakravarti, R. Weaver, S.S.K. Iper, T. Hook, A. Sierakowski, K. Winstel, J. Spieck, D. Prakash, X. Tian, N. Robson, H. Wang, W. Stillman, J. Rice, B. Flietner, L. Jung, S. Iyer

{"title":"Device equivalence of logic performance in 0.18 /spl mu/m and extension to 0.13 /spl mu/m embedded DRAM technology","authors":"S. Chakravarti, R. Weaver, S.S.K. Iper, T. Hook, A. Sierakowski, K. Winstel, J. Spieck, D. Prakash, X. Tian, N. Robson, H. Wang, W. Stillman, J. Rice, B. Flietner, L. Jung, S. Iyer","doi":"10.1109/VTSA.2001.934493","DOIUrl":"https://doi.org/10.1109/VTSA.2001.934493","url":null,"abstract":"The embedded DRAM (eDRAM) technology can offer significant advantages in terms of performance and power consumption by combining a high bandwidth DRAM macro on the same chip as logic/analog circuits. However, it is a challenge for a device engineer to ensure that electrical parameters and performance of CMOS logic devices and SRAM yield are not compromised in the integration process and at the same time DRAM leakage and retention objectives are met. This paper reports a manufacturable 0.18 /spl mu/m eDRAM technology, where this task has been successfully accomplished. The characteristics of logic and array devices operating from a power supply of 1.8 V are presented. The eDRAM logic device characteristics are compared with 'logic-only' (base) process devices and are found to be comparable. DRAM device characteristics, leakage and retention data measured on test structures are also shown which satisfy the temperature range of operation from 0/spl deg/C to 105/spl deg/C of the product.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126206740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Key specifications and implementation of WCDMA receiver WCDMA接收机的关键规格与实现

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 2001-04-18 DOI: 10.1109/VTSA.2001.934480

B. Ramachandran, J. Vasa, A. Loke

引用次数: 8

1T1C FRAM

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934488

Kinam Kim

引用次数: 0

Thickness measurement of ultra-thin gate dielectrics under inversion condition 反演条件下超薄栅极电介质的厚度测量

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI: 10.1109/VTSA.2001.934522

W.J. Zhu, M. Khare, J. Snare, P. Varekamp, S. Ku, P. Agnello, T. Chen, T. Ma

引用次数: 4