S. Chakravarti, R. Weaver, S.S.K. Iper, T. Hook, A. Sierakowski, K. Winstel, J. Spieck, D. Prakash, X. Tian, N. Robson, H. Wang, W. Stillman, J. Rice, B. Flietner, L. Jung, S. Iyer
{"title":"Device equivalence of logic performance in 0.18 /spl mu/m and extension to 0.13 /spl mu/m embedded DRAM technology","authors":"S. Chakravarti, R. Weaver, S.S.K. Iper, T. Hook, A. Sierakowski, K. Winstel, J. Spieck, D. Prakash, X. Tian, N. Robson, H. Wang, W. Stillman, J. Rice, B. Flietner, L. Jung, S. Iyer","doi":"10.1109/VTSA.2001.934493","DOIUrl":null,"url":null,"abstract":"The embedded DRAM (eDRAM) technology can offer significant advantages in terms of performance and power consumption by combining a high bandwidth DRAM macro on the same chip as logic/analog circuits. However, it is a challenge for a device engineer to ensure that electrical parameters and performance of CMOS logic devices and SRAM yield are not compromised in the integration process and at the same time DRAM leakage and retention objectives are met. This paper reports a manufacturable 0.18 /spl mu/m eDRAM technology, where this task has been successfully accomplished. The characteristics of logic and array devices operating from a power supply of 1.8 V are presented. The eDRAM logic device characteristics are compared with 'logic-only' (base) process devices and are found to be comparable. DRAM device characteristics, leakage and retention data measured on test structures are also shown which satisfy the temperature range of operation from 0/spl deg/C to 105/spl deg/C of the product.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2001.934493","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The embedded DRAM (eDRAM) technology can offer significant advantages in terms of performance and power consumption by combining a high bandwidth DRAM macro on the same chip as logic/analog circuits. However, it is a challenge for a device engineer to ensure that electrical parameters and performance of CMOS logic devices and SRAM yield are not compromised in the integration process and at the same time DRAM leakage and retention objectives are met. This paper reports a manufacturable 0.18 /spl mu/m eDRAM technology, where this task has been successfully accomplished. The characteristics of logic and array devices operating from a power supply of 1.8 V are presented. The eDRAM logic device characteristics are compared with 'logic-only' (base) process devices and are found to be comparable. DRAM device characteristics, leakage and retention data measured on test structures are also shown which satisfy the temperature range of operation from 0/spl deg/C to 105/spl deg/C of the product.