Tailoring logic CMOS for RF applications

The radio-frequency (RF) potential of logic CMOS is assessed in this paper. Steps towards an optimum RF performance are explained. Devices are optimized for the frequency responses (f/sub T/ and f/sub max/), the minimum noise figure (F/sub min/), and the 1/f-noise based on device layout, bias conditions, and type of gate dielectric. Those steps are verified through a detailed study of IBM's 0.18 /spl mu/m CMOS logic technology. The identification of high RF performance of logic CMOS technology points out the advantage over dedicated RF CMOS technology.