New stack gate insulator structure strongly reduces FIBL effect

Abstract

Recent studies have shown that by adapting high-k gate dielectric, deep sub-micron MOSFET suffers short channel effect caused by the fringing electric fields from gate to source/drain regions. In this work, a simulation-based analysis of multiple gate stack structure with channel length as low as 50 nm is presented. The new stack gate structure can be optimized for reducing the undesirable fringing induced barrier lowering effect of a high-k gate dielectric device.