Design of k-WTA/Sorting network using maskable WTA/MAX circuit

This paper presents a novel circuit for the k-WTA/Sorting network that processes eight 8-bit patterns. This design is based on a maskable WTA/MAX circuit which generates maximum value and winner with maskable skill. It can obtain the whole system functions: WTA/MAX/k-WTA/Sorter without adding any extra components. The proposed hardware architecture features layout regularity and interconnection compactness, thus it can be exploited to obtain a small and efficient hardware implementation. The chip was fabricated with the TSMC 0.35/spl square/m SPQM CMOS process. Experimental results indicate this chip can work up to 66 MHz with power consumption less than 10 mW at 3.3 V supply voltage. This design is suitable for VLSI implementation. It can also be applied well when being embedded in digital signal processors.