{"title":"A 5 GHz band CMOS low noise amplifier with a 2.5 dB noise figure","authors":"Eric H. Westerwick","doi":"10.1109/VTSA.2001.934525","DOIUrl":null,"url":null,"abstract":"The noise performance of a radio receiver is largely determined by the noise figure of the first-stage amplifier. The amplifier also must have high gain and remain linear when presented with large input signals to minimize distortion in the receiver output. Amplifiers having high performance in the 5 GHz band are often composed of discrete components or integrated using GaAs or Si bipolar technologies. This work demonstrates a fully integrated high performance 5.25 GHz LNA realized with a 0.25 /spl mu/m linear CMOS technology.","PeriodicalId":388391,"journal":{"name":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"56","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTSA.2001.934525","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 56
Abstract
The noise performance of a radio receiver is largely determined by the noise figure of the first-stage amplifier. The amplifier also must have high gain and remain linear when presented with large input signals to minimize distortion in the receiver output. Amplifiers having high performance in the 5 GHz band are often composed of discrete components or integrated using GaAs or Si bipolar technologies. This work demonstrates a fully integrated high performance 5.25 GHz LNA realized with a 0.25 /spl mu/m linear CMOS technology.