A lithographically-friendly 6F/sup 2/ DRAM cell

Abstract

Ever-decreasing chip size in successive generations of DRAM has been largely achieved by lithographic ground rule scaling. Recently, a combination of device performance issues and uncertainty in future lithographic scaling have led to the investigation of novel array cell architectures, as well as fundamental changes in the array transistor itself. These new cell architectures present a unique challenge for optical lithography, especially when implemented at aggressive ground rules. In this paper, we discuss how lithography can influence the design of a DRAM array cell, and present lithographic results from a 512 Mb, 6F/sup 2/ DRAM technology practiced at 0.13 /spl mu/m ground rules. We discuss the methodology of "lithography-friendly" cell design in the context of sub-8F/sup 2/ arrays, and describe a multiple exposure technique for capacitor formation in the sub-8F/sup 2/ regime.