低温下的纳米级CMOS:设计、可靠性和缩放趋势

2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517) Pub Date : 1900-01-01 DOI:10.1109/VTSA.2001.934473

B. Yu, H. Wang, C. Riccobene, Hyeon-Seag Kim, Q. Xiang, M. Lin, Leland Chang, C. Hu

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引用次数: 12

摘要

只要能在室温下提高集成电路的性能，半导体工业就没有动力去实际应用低温操作。然而，随着CMOS接近缩放极限，冷却芯片操作成为一个有吸引力的选择。本文探讨了IC温度“缩放”的可行性及其对低于50纳米CMOS世代的器件性能和可靠性的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Nanoscale CMOS at low temperature: design, reliability, and scaling trend

The semiconductor industry is not motivated to make practical use of cryogenic operation as long as IC performance could be improved at room temperature. However, as CMOS approaches the scaling limits, cooled chip operation becomes an attractive alternative. This paper explores the feasibility of IC temperature "scaling" and its implications to device performance and reliability for sub-50 nm CMOS generations.

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2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517)

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