Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-/spl mu/m partially-depleted SOI salicide CMOS technology

Abstract

Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-/spl mu/m partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by an ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.