ESD protection strategy for sub-quarter-micron CMOS technology: gate-driven design versus substrate-triggered design

Abstract

The operation principles of gate-driven design and substrate-triggered design for ESD (Electrostatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18 /spl mu/m and 0.35 /spl mu/m CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices and is better than the gate-driven design. The HBM (Human-Body-Model) ESD level of NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the subquarter-micron CMOS process.