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ESSCIRC 76: 2nd European Solid State Circuits Conference最新文献

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A New Circuit Technique in Voltage and Temperature Compensated Emitter-Coupled Logic 一种电压温度补偿型发射耦合逻辑电路新技术
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469244
W. Wilhelm, K. Schon
{"title":"A New Circuit Technique in Voltage and Temperature Compensated Emitter-Coupled Logic","authors":"W. Wilhelm, K. Schon","doi":"10.1109/ESSCIRC.1976.5469244","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469244","url":null,"abstract":"Starting with well-known methods of voltage and temperature compensated circuits a new area saving circuit design with good compensation results is presented.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114320802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Schottky Collector Integrated Injection Logic 肖特基收集器集成注入逻辑
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469091
S. Blackstone, R. Mertens
{"title":"Schottky Collector Integrated Injection Logic","authors":"S. Blackstone, R. Mertens","doi":"10.1109/ESSCIRC.1976.5469091","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469091","url":null,"abstract":"A very simple technology has been fabricated which displays speeds better than conventional I2L and a packing density comparable to oxide isolation. Furthermore, the question, or downward current gain is shown both theoretically and experimentally to be a controllable problem.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114868316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Power D-MOS Logic 低功耗D-MOS逻辑
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469088
M. Declercq, T. Laurent
{"title":"Low-Power D-MOS Logic","authors":"M. Declercq, T. Laurent","doi":"10.1109/ESSCIRC.1976.5469088","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469088","url":null,"abstract":"A simple silicon-gate D-MOS process suitable for enhancement-depletion logic is described. Design and performance of D-MOS logic circuits are investigated and compared to standard E/D logic. Practical results of a low-power ring oscillator are presented.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128468659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Objectives for Integrated Circuit Tolerance Design 集成电路公差设计的目标
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469098
P. R. Adby
{"title":"Objectives for Integrated Circuit Tolerance Design","authors":"P. R. Adby","doi":"10.1109/ESSCIRC.1976.5469098","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469098","url":null,"abstract":"The objectives of statistical tolerance design are established in relation to the practical design situation for large integrated circuits.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133007959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CIRCEC: A Cost-Effective Computer Program for Circuit Design CIRCEC:一个具有成本效益的电路设计计算机程序
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469073
D. Herrerias, A. Labarthe, G. Guerin
{"title":"CIRCEC: A Cost-Effective Computer Program for Circuit Design","authors":"D. Herrerias, A. Labarthe, G. Guerin","doi":"10.1109/ESSCIRC.1976.5469073","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469073","url":null,"abstract":"CIRCEC is an interactive general puirpose simulation program performing AC, DC and transient analysis of non-linear electronic circuits. A library of user-defined FORTRAN models is available. CIRCEC is easy to use, economical and allows simulation of a large range of circuits.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121224581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimal Use of Junction Isolation for Photodetection in Monolithic Integrated Optoelectronic Circuits 结隔离在单片集成光电子电路光检测中的最佳应用
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/esscirc.1976.5469238
K. Berchtold, S. Dermitzakis, J. Suri
{"title":"Optimal Use of Junction Isolation for Photodetection in Monolithic Integrated Optoelectronic Circuits","authors":"K. Berchtold, S. Dermitzakis, J. Suri","doi":"10.1109/esscirc.1976.5469238","DOIUrl":"https://doi.org/10.1109/esscirc.1976.5469238","url":null,"abstract":"The concept of optimal use of junction isolation for photodetection in integrated circuits containing a detector element and associated amplifier and logic circuits is described.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127714221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon on Sapphire technology 蓝宝石上硅技术
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469255
Y. Nishi
{"title":"Silicon on Sapphire technology","authors":"Y. Nishi","doi":"10.1109/ESSCIRC.1976.5469255","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469255","url":null,"abstract":"access memory, a programmable logic array, a nonvolatile memory etc. The primary difficulties of the SOS structure, such as obtaining the epitaxial silicon films with acceptable electrical characteristics and with reasonably good crystal perfection, seem to be solved from the practical point of view for fabrica¬ tion of MOS transistors on SOS wafer. Basic superiority of the SOS structure compared with the bulk silicon structure has been confirmed through the high density CMOS LSI without any parasitic bipolar transistor effects between n-channel and p-channel transistors, and n-channel MOS LSI with higher speed due to decrease in parasitic capacitance of interconnections of both diffused layers and aluminum and/or polycrystal silicon layers. However, there still remain a number of phenomena which should be revealed prior to development of more advanced version of SOS LSIs. This paper will review the present state of the art, and discuss feasibility of SOS technology, looking at the following matters of interest.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130309626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
EPISODE, A Set of Tools Oriented to Logic Integrated Circuit Design Verification and Testing 一套面向逻辑集成电路设计验证与测试的工具
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469075
C. Lam, J. Thuel, R. Tulloue
{"title":"EPISODE, A Set of Tools Oriented to Logic Integrated Circuit Design Verification and Testing","authors":"C. Lam, J. Thuel, R. Tulloue","doi":"10.1109/ESSCIRC.1976.5469075","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469075","url":null,"abstract":"The main features of the EPISODE system of logic simulators are described. Its use during circuit design process and its extensions for the simulation of very large scale integrated circuits are presented.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123175687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 16K MOS RAM in Double-Polysilicon Technology 双多晶硅技术中的16K MOS RAM
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469235
R. Mitterer, B. Rehn
{"title":"A 16K MOS RAM in Double-Polysilicon Technology","authors":"R. Mitterer, B. Rehn","doi":"10.1109/ESSCIRC.1976.5469235","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469235","url":null,"abstract":"A 16 384 bit-RAM with a chip area of 23 mm2, using double-polysilicon technology, is presented. The device with a 300 ns access time fits in a 16 pin package. Circuit Principles for cell and sense amplifier and read-modify-write and page-mode operation are treated.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131338018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
ASTEC 3, A User Oriented Circuit Analysis Program 面向用户的电路分析程序
ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI: 10.1109/ESSCIRC.1976.5469074
M. Heydemann
{"title":"ASTEC 3, A User Oriented Circuit Analysis Program","authors":"M. Heydemann","doi":"10.1109/ESSCIRC.1976.5469074","DOIUrl":"https://doi.org/10.1109/ESSCIRC.1976.5469074","url":null,"abstract":"This paper describes a general purpose circuit analysis program which features DC, AC and transient, nominal and statistical analysis of arbitrary non linear circuits which have been developed in the C.E.A. for its internal needs in circuit design.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130529487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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