Low-Power D-MOS Logic

ESSCIRC 76: 2nd European Solid State Circuits Conference Pub Date : 1976-09-01 DOI:10.1109/ESSCIRC.1976.5469088

M. Declercq, T. Laurent

引用次数: 0

Abstract

A simple silicon-gate D-MOS process suitable for enhancement-depletion logic is described. Design and performance of D-MOS logic circuits are investigated and compared to standard E/D logic. Practical results of a low-power ring oscillator are presented.

查看原文本刊更多论文

低功耗D-MOS逻辑

描述了一种适用于增强耗尽逻辑的简单硅栅D-MOS工艺。研究了D- mos逻辑电路的设计和性能，并与标准E/D逻辑进行了比较。给出了一种小功率环形振荡器的实际效果。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

ESSCIRC 76: 2nd European Solid State Circuits Conference

自引率

0.00%

发文量