{"title":"一套面向逻辑集成电路设计验证与测试的工具","authors":"C. Lam, J. Thuel, R. Tulloue","doi":"10.1109/ESSCIRC.1976.5469075","DOIUrl":null,"url":null,"abstract":"The main features of the EPISODE system of logic simulators are described. Its use during circuit design process and its extensions for the simulation of very large scale integrated circuits are presented.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"EPISODE, A Set of Tools Oriented to Logic Integrated Circuit Design Verification and Testing\",\"authors\":\"C. Lam, J. Thuel, R. Tulloue\",\"doi\":\"10.1109/ESSCIRC.1976.5469075\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The main features of the EPISODE system of logic simulators are described. Its use during circuit design process and its extensions for the simulation of very large scale integrated circuits are presented.\",\"PeriodicalId\":378614,\"journal\":{\"name\":\"ESSCIRC 76: 2nd European Solid State Circuits Conference\",\"volume\":\"80 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1976-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 76: 2nd European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1976.5469075\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 76: 2nd European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1976.5469075","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
EPISODE, A Set of Tools Oriented to Logic Integrated Circuit Design Verification and Testing
The main features of the EPISODE system of logic simulators are described. Its use during circuit design process and its extensions for the simulation of very large scale integrated circuits are presented.