{"title":"蓝宝石上硅技术","authors":"Y. Nishi","doi":"10.1109/ESSCIRC.1976.5469255","DOIUrl":null,"url":null,"abstract":"access memory, a programmable logic array, a nonvolatile memory etc. The primary difficulties of the SOS structure, such as obtaining the epitaxial silicon films with acceptable electrical characteristics and with reasonably good crystal perfection, seem to be solved from the practical point of view for fabrica¬ tion of MOS transistors on SOS wafer. Basic superiority of the SOS structure compared with the bulk silicon structure has been confirmed through the high density CMOS LSI without any parasitic bipolar transistor effects between n-channel and p-channel transistors, and n-channel MOS LSI with higher speed due to decrease in parasitic capacitance of interconnections of both diffused layers and aluminum and/or polycrystal silicon layers. However, there still remain a number of phenomena which should be revealed prior to development of more advanced version of SOS LSIs. This paper will review the present state of the art, and discuss feasibility of SOS technology, looking at the following matters of interest.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Silicon on Sapphire technology\",\"authors\":\"Y. Nishi\",\"doi\":\"10.1109/ESSCIRC.1976.5469255\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"access memory, a programmable logic array, a nonvolatile memory etc. The primary difficulties of the SOS structure, such as obtaining the epitaxial silicon films with acceptable electrical characteristics and with reasonably good crystal perfection, seem to be solved from the practical point of view for fabrica¬ tion of MOS transistors on SOS wafer. Basic superiority of the SOS structure compared with the bulk silicon structure has been confirmed through the high density CMOS LSI without any parasitic bipolar transistor effects between n-channel and p-channel transistors, and n-channel MOS LSI with higher speed due to decrease in parasitic capacitance of interconnections of both diffused layers and aluminum and/or polycrystal silicon layers. However, there still remain a number of phenomena which should be revealed prior to development of more advanced version of SOS LSIs. This paper will review the present state of the art, and discuss feasibility of SOS technology, looking at the following matters of interest.\",\"PeriodicalId\":378614,\"journal\":{\"name\":\"ESSCIRC 76: 2nd European Solid State Circuits Conference\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1976-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 76: 2nd European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1976.5469255\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 76: 2nd European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1976.5469255","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
access memory, a programmable logic array, a nonvolatile memory etc. The primary difficulties of the SOS structure, such as obtaining the epitaxial silicon films with acceptable electrical characteristics and with reasonably good crystal perfection, seem to be solved from the practical point of view for fabrica¬ tion of MOS transistors on SOS wafer. Basic superiority of the SOS structure compared with the bulk silicon structure has been confirmed through the high density CMOS LSI without any parasitic bipolar transistor effects between n-channel and p-channel transistors, and n-channel MOS LSI with higher speed due to decrease in parasitic capacitance of interconnections of both diffused layers and aluminum and/or polycrystal silicon layers. However, there still remain a number of phenomena which should be revealed prior to development of more advanced version of SOS LSIs. This paper will review the present state of the art, and discuss feasibility of SOS technology, looking at the following matters of interest.