{"title":"低功耗D-MOS逻辑","authors":"M. Declercq, T. Laurent","doi":"10.1109/ESSCIRC.1976.5469088","DOIUrl":null,"url":null,"abstract":"A simple silicon-gate D-MOS process suitable for enhancement-depletion logic is described. Design and performance of D-MOS logic circuits are investigated and compared to standard E/D logic. Practical results of a low-power ring oscillator are presented.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low-Power D-MOS Logic\",\"authors\":\"M. Declercq, T. Laurent\",\"doi\":\"10.1109/ESSCIRC.1976.5469088\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A simple silicon-gate D-MOS process suitable for enhancement-depletion logic is described. Design and performance of D-MOS logic circuits are investigated and compared to standard E/D logic. Practical results of a low-power ring oscillator are presented.\",\"PeriodicalId\":378614,\"journal\":{\"name\":\"ESSCIRC 76: 2nd European Solid State Circuits Conference\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1976-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 76: 2nd European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1976.5469088\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 76: 2nd European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1976.5469088","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A simple silicon-gate D-MOS process suitable for enhancement-depletion logic is described. Design and performance of D-MOS logic circuits are investigated and compared to standard E/D logic. Practical results of a low-power ring oscillator are presented.
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