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1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration最新文献

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A testing approach for WSI globally interconnected parallel architectures WSI全球互联并行架构的测试方法
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255259
G. Buonanno, D. Sciuto, Fabio Zanicotti
{"title":"A testing approach for WSI globally interconnected parallel architectures","authors":"G. Buonanno, D. Sciuto, Fabio Zanicotti","doi":"10.1109/ICWSI.1993.255259","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255259","url":null,"abstract":"A testability analysis and a testing approach for interconnection topologies are presented. The testing approach is based on the analysis of controllability and observability of the architecture, given the cells functions and the interconnection topology. For the architectures directly derived from a data flow graph, a functional fault model is adopted. A specific fault model is derived for multistage interconnection networks. The switching matrices can be in a number of different states, depending on the number of input/output lines. In general, only a small number of states is necessary for correct computation, and these are the only states considered legal. A cell is defined to be faulty if its switching matrix can reach a nonlegal state.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123728422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Characterization of the broadband transmission behavior of interconnections on silicon substrates 硅衬底互连宽带传输特性的表征
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255251
S. Zaage, E. Groteluschen
{"title":"Characterization of the broadband transmission behavior of interconnections on silicon substrates","authors":"S. Zaage, E. Groteluschen","doi":"10.1109/ICWSI.1993.255251","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255251","url":null,"abstract":"Some characteristics of the transmission behavior of interconnections on conductive silicon substrates are presented. With regard to the signal propagation on high-speed digital circuits the broadband behavior of the lines is of special interest. The characteristic impedance and the propagation constant of the lines are determined experimentally by microwave measurements. The influence of the line geometry, the substrate resistivity and the signal frequency on the transmission behavior are clarified. Based on the results of the measurements, the suitability of the conventional RLC line model for time-domain simulations of the transmission characteristics of interconnections on silicon substrates is investigated.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133129794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Interconnection networks with fault-tolerance properties 具有容错特性的互连网络
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255257
M. Slimane-kadi, A. Boubekeur, G. Saucier
{"title":"Interconnection networks with fault-tolerance properties","authors":"M. Slimane-kadi, A. Boubekeur, G. Saucier","doi":"10.1109/ICWSI.1993.255257","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255257","url":null,"abstract":"A flexible programmable switch is proposed to realize interconnection networks. The programming capabilities from the periphery of the network allow the external elements to control it efficiently. For fault tolerant capabilities, two strategies are considered. The first uses this programming facility to overcome both connection and switch faults in a crossbar matrix. The second is restricted to fault tolerance with regard to the switches, and is applied to an omega network.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117308055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An advanced MCM associative string processor 一个先进的MCM关联字符串处理器
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255266
I. Jalowiecki, R. Lea, D. Pedder
{"title":"An advanced MCM associative string processor","authors":"I. Jalowiecki, R. Lea, D. Pedder","doi":"10.1109/ICWSI.1993.255266","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255266","url":null,"abstract":"The HASP4001 hybrid wafer scale integration (HWSI) device, optimized for massively parallel processing, is described. It is a large-area silicon-on-silicon multichip module (MCM-D). The design is based on the experience gained in the implementation of a previous-generation massively parallel computer. It is shown that the resulting module is a significantly more cost-effective system component, minimizing board area and enhancing performance. It is shown that the HWSI incorporates many of the same techniques adopted for the monolithic WSI version, ensuring reliable implementation suitable for medium scale production.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Interconnection technologies for multichip assemblies (ITMA)-A UK Information Technology Engineering Directorate hybrid wafer scale project 多芯片组件互连技术(ITMA)-英国信息技术工程理事会混合晶圆规模项目
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255269
D. Pedder
{"title":"Interconnection technologies for multichip assemblies (ITMA)-A UK Information Technology Engineering Directorate hybrid wafer scale project","authors":"D. Pedder","doi":"10.1109/ICWSI.1993.255269","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255269","url":null,"abstract":"The Interconnection technology for multichip assemblies (ITMA) project is addressing the application of a silicon-substrate-based multichip module (MCM) technology to the requirements of parallel computing applications in the UK. The program involves activities on MCM design methodology, silicon substrate process technology, device assembly, module packaging technology, the design of VLSI devices specifically for MCM applications, and the implementation of advanced MCM demonstrator modules in parallel computing systems. The objectives of the ITMA project are described, and the technologies employed within the project to realize high-performance MCMs and hybrid wafer scale integration (HWSI) modules are reviewed.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129258838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Three dimensional hybrid wafer scale integration using the GE high density interconnect technology 采用GE高密度互连技术的三维混合晶圆级集成
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255247
R.J. Wojnarowski, R. Fillion, B. Gorowitz, R. Saia
{"title":"Three dimensional hybrid wafer scale integration using the GE high density interconnect technology","authors":"R.J. Wojnarowski, R. Fillion, B. Gorowitz, R. Saia","doi":"10.1109/ICWSI.1993.255247","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255247","url":null,"abstract":"A three-dimensional multichip technology is discussed. It provides solutions to the interconnect and packaging problems associated with very high density requirements of large distributed processing systems and large solid-state memory systems. The technical approach involves an extension of the 2D multichip module (MCM) circuits fabricated with the high-density-interconnect (HDI) overlay technology. These are then stacked and interconnected with a modified version of the 2D HDI interconnect process applied to the side edges of the stack. Test structures and a stack of function circuit circuits are fabricated and tested. The features of this approach, a description of the process, and the results of tests on the demonstration vehicles are presented.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116006755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
The development of the WASP 3 processor WASP - 3处理器的开发
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255277
I. Jalowiecki, S. Hedge, R. Williams
{"title":"The development of the WASP 3 processor","authors":"I. Jalowiecki, S. Hedge, R. Williams","doi":"10.1109/ICWSI.1993.255277","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255277","url":null,"abstract":"The ASP (associative string processor) is a massively parallel, fault tolerant, fully associative processor designed for the implementation of very compact, easily extensible, modular low-multiple-instruction, multiple-data/high-single-instruction multiple-data (low-MIMD/high-SIMD) parallel processing systems. It is capable of supporting real-world applications of continuous data input and tightly integrated numeric and symbolic computations. The ASP module architecture and the wafer-scale (WASP-3) concept are described.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122656127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
An approach for reducing the programming cost of soft switches in reconfigurable WSI arrays 一种降低可重构WSI阵列软开关编程成本的方法
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255255
T. Liu, F. Lombardi
{"title":"An approach for reducing the programming cost of soft switches in reconfigurable WSI arrays","authors":"T. Liu, F. Lombardi","doi":"10.1109/ICWSI.1993.255255","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255255","url":null,"abstract":"Discusses the cost involved in the programming of nonpermanent (soft) switching elements in an augmented interconnection network for reconfigurable two-dimensional wafer scale integration (WSI) arrays. The formulation and characterization of two different figures for evaluating the cost of switch programming are given. A new cost, referred to as the adjusted cost, is introduced for establishing a relationship between the programming process and the switching modes of the target array. Reduction in cost is achieved by two techniques: redundancy reduction given by the number of times a switch is programmed in a tree; and a relaxation technique, referred to as compression, in which each of the two cost figures is primarily considered for reduction.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117350346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimizing multipliers for WSI 优化WSI乘数
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255270
T. K. Callaway, E. Swartzlander
{"title":"Optimizing multipliers for WSI","authors":"T. K. Callaway, E. Swartzlander","doi":"10.1109/ICWSI.1993.255270","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255270","url":null,"abstract":"For arithmetic circuits, it is important to maximize the speed and to minimize the power consumption, which may be accomplished by minimizing the product of the delay and the power consumption. The authors discuss the speed and the number of logic transitions (a measure of power dissipation for static CMOS circuits) of several different parallel multipliers. The circuits are constructed with inverters and two- to four-input AND and OR gates. Extensive simulation is used to evaluate their switching characteristics, and the results of the simulations are used to rank the multipliers on speed, size, and the number of logic transitions.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117023804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Algorithmic bus and circuit layout for wafer-scale integration and multichip modules 圆片级集成和多芯片模块的算法总线和电路布局
1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration Pub Date : 1993-01-20 DOI: 10.1109/ICWSI.1993.255264
G. Chapman, R. Hobson
{"title":"Algorithmic bus and circuit layout for wafer-scale integration and multichip modules","authors":"G. Chapman, R. Hobson","doi":"10.1109/ICWSI.1993.255264","DOIUrl":"https://doi.org/10.1109/ICWSI.1993.255264","url":null,"abstract":"In both laser-link-oriented wafer scale integration (WSI) and multichip modules (MCMs), arrays of devices may be ordered in such a way that the actual physical position of devices is extremely important. Traditional graphic-based design systems are not well suited for such applications. Examples are presented illustrating the effectiveness of a C-based design language (CDL) for WSI laser-link bus placement and MCM chip placement and interconnection. A brief description of the CDL platform is included.<<ETX>>","PeriodicalId":377227,"journal":{"name":"1993 Proceedings Fifth Annual IEEE International Conference on Wafer Scale Integration","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115362239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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